Introduction to the StrongARM                        Revision 2, 31-Jul-96
=============================


The StrongARM 110 is a new high-performance processor from Digital
Semiconductor. It offers performance improvements over the ARM710 ranging
from 100% to 1000%, depending on the application.

A StrongARM processor card will available for the Risc PC later this year.
It will come with a new ROM set containing RISC OS 3.70, a new StrongARM-
compatible version of RISC OS. These documents provide information on
writing software, and modifying existing software, for StrongARM-based
machines.


Significant StrongARM features
------------------------------

    * 202MHz core clock
      
    * 5-stage pipeline (Fetch, Issue, Execute, Buffer, Write)
      
    * Separate 16K write-back data cache and 16K instruction cache
      
    * 8 entry write buffer, each entry holding 1-16 bytes
      
    * Fast 32 and 64 bit result multiply instructions
    
    * Averages fewer cycles per instruction than previous ARMs
      

Incompatibilities
-----------------
The StrongARM has two significant differences from previous ARMs that
can affect existing programs. Firstly, the split caches mean that
instructions written into memory may linger in the data cache, and not
be in real memory when the instruction cache comes to fetch them. Likewise
if some code is already in the instruction cache, and it is altered, the
changed code will not be noticed. Thus existing self-modifying code and
dynamic code creation or loading will generally not work.

RISC OS 3.7 provides a call to synchronise the instruction and data caches,
but this is a slow operation on the StrongARM. Self-modifying code should
therefore be avoided. The most common failures here arise from custom
SWI veneers that assemble code on the stack, dynamic code loading
and linking and custom code squeezing and encryption.

The other significant StrongARM change is that storing the PC to memory
(using STR or STM) stores PC+8 rather than PC+12. This can generally be
catered for by judicious use of NOPs to allow for both possibilities.
This affects, for example, APCS stack backtraces and vector claimants
(the example code on PRM page 1-107 will not work, for example).

There are other differences that are only likely to be encountered by
low-level system code.

Most applications will run unmodified on StrongARM, especially those
written in C and BASIC, but some code will inevitably need modification.


What to read next
-----------------
The file "Guidelines" gives a general overview of guidelines for authoring
software for use on StrongARM based machines.

The file "SAsupport" details the new and extended SWIs in RISC OS 3.7
to support the StrongARM.

The file "MiscChange" details other changes in RISC OS 3.7 that are not
related to StrongARM compatibility.

The file "Performanc" gives hints on how to improve performance of code
on StrongARM.

The file "FIQs" shows how to get FIQ code working on StrongARM.
