
*** Techie details

Below I briefly detail how each section of SI gives its results - for
more details look at the code. The important routines are PROCcalcsi
and PROCdisplaysi.

Available RAM - MEMC tells you the page size, and so total RAM can be
        easily worked out. Uses OS_ReadMemMapInfo call.

Available ROM - tricky ... Currently we just guess based on the OS 
        version.

5th Column ROMs - you don't notice this feature unless you have
        5th column ROMs, but the program finds the number of extension
        ROMs with Podule_ReturnNumber, and then counts the total size
        of code/data using Podule_EnumerateChunksWithInfo - so you
        get the cumulative total of data - not the capacity of the 
        ROMs when full ...

ROM Speed - we know the number of n-cycles per ROM access (from MEMC),
        so this is multiplied by the current RAM Speed.

RAM Speed - the operating system works this out on startup, and so we
        just ask nicely (zero page location).

DRAM refresh - a MEMC returned result (you use OS_UpdateMEMC SWI for
        all these MEMC read/writes)

MEMC type - zero page location gives MEMC1 or MEMC1a type, as worked
        out by the OS.

IOC type - unknown - call it IOC1 !

IOEB type - under RO3.xx an OS_ReadSysInfo call returns this, and 
        whether one is present or not. IOEB can only exist on RO3.xx
        and greater machines.

VIDC type - assume a VIDC1a (most machines), unless an A500 computer.
        The A500 is ID'd using the fact that 99% of all the A500s 
        have RTCs with 30 second precision. A500s have VIDC1 chips.
        Actually this test doesn't work because of the OS simulating
        the RTC 8-( Instead we use the keyboard ID byte ... If you
        have an A500 with a new keyboard - tough!

ARM type - see the assembler code at the end of the main program.
        ARM1 chips don't do multiply, ARM2 chips don't do SWP 
        instructions, ARM250 chips don't have coprocessor 15
        (internal), and all later chips can be ID'd from a status
        register inside coprocessor 15.

FPA type - Again, a coprocessor transfer as defined in the Acorn
        FP specs (see PRMs) which can ID software/hardware FP
        details.

Periph Ctrlr - OS_ReadSysInfo call under RO3 can ID the 82C710 or
        82C711 peripheral controller chip which handles the IDE
        interface, etc.

LCD ASIC - only present in A4 portables, this chip does the
        fancy 15-greyscale display, and is ID'd using OS_ReadSysInfo

RO ver - Read from OS_Byte,0,0

Video screen mode - read from the BASIC 'MODE' command, and a 
        selection of OS_ReadModeVariable calls

Unique machine ID - only present on modern RO3 machines (A3010/3020/
        A4000/5000/A4/etc) read using OS_ReadSysInfo call

Details of most of the calls listed above can be found in the RISC OS3
Programmers Reference Manual, available from your local Acorn Dealer 8-)

*** Original Authors Notes

 1) Instructions timings are accurate to within:

                 4 * MCLK
                 --------   
                     i
 
          where 
               i    is the number of instructions tested
               MCLK is the system clock (125 nS on an 8 MHz machine)

    ARM instructions are therfore calculated to within 2 nS +- 2%
 2) ARM Speed in MIPS is calculated as the average number of each
    instruction Group in a test sample of 1000 instructions
 3) IOC and VIDC types remain Unknown at present
 4) Checks are made for all processors known to date. ie. ARM 1,2 and 3
 5) Interrupts and DMA requests are stopped whilst calculations are
    taking place
 6) Looped instructions are calculated as one instruction of the specific
    Group + one Group 1 + one group 4 instruction
 7) Instruction timings are calculated during Video Flyback, and are
    therefore dependant on the Video Flyback period and DRAM refresh
    (large modes with no vertical boarders will affect results)
 8) Group 1a results on ARM 2's do not take account of the hardware bug
    (instructions take 24 S cycles rather than the maximum of 16)
 9) Instruction indexes are relative to a perfect ARM 2 running at 8 MHz
10) FPU instruction speeds are calculated by either 3, 16 or 80
    instructions depending upon the instruction in question.  
11) FPU instructions are calculated to within 167 nS, 31 nS or 6 ns +- 2%
    dependent upon the instruction
11) FPU indexes include both register values and immediate values in the
    form #1.0
12) FPU speed in FLOPS is calculated as the total number of instructions
    divided by the time taken, this does not take account of common
    instructions
13) All FPU calculations with the exception of STF and LDF are done in
    extended precision.  STF and LDF are packed decimal precision

