      
      =============================================================================
      
      		SPICE3 Version 3f3 User's Manual
      
      			 May, 1993
      
        T. QuarlesA.R.Newton, D.O.Pederson, A.Sangiovanni-Vincentelli
      
         Department of Electrical Engineering and Computer Sciences
      		 University of California
      
      		   Berkeley, Ca., 94720
      
      Copyright 1990, 1991, 1992, 1993 Regents of the University of California. All
      rights reserved.
      
      This manual may be reproduced in whole or in part without permission for any
      purpose other than resale for profit, if this copyright notice is included;
      personal, educational, or internal business use is specifically permitted as
      long as the copyright notice is preserved.
      
      
      =============================================================================
      
      
      TABLE OF CONTENTS
      
      0. Release Notes
      
      1.  INTRODUCTION
        1.1.  TYPES OF ANALYSIS
          1.1.1.  DC Analysis
          1.1.2.  AC Small-Signal Analysis
          1.1.3.  Transient Analysis
          1.1.4.  Pole-Zero Analysis
          1.1.5.  Small-Signal Distortion Analysis
          1.1.6.  Sensitivity Analysis
          1.1.7.  Noise Analysis
        1.2.  ANALYSIS AT DIFFERENT TEMPERATURES
        1.3.  CONVERGENCE
      
      2.  CIRCUIT DESCRIPTION
        2.1.  GENERAL STRUCTURE AND CONVENTIONS
        2.2.  TITLE LINE, COMMENT LINES AND .END LINE
          2.2.1.  Title Line
          2.2.2.  .END Line
          2.2.3.  Comments
        2.3.  DEVICE MODELS
        2.4.  SUBCIRCUITS
          2.4.1.  .SUBCKT Line
          2.4.2.  .ENDS Line
          2.4.3.  Subcircuit Calls
        2.5.  COMBINING FILES: .INCLUDE LINES
      
      3.  CIRCUIT ELEMENTS AND MODELS
        3.1.  ELEMENTARY DEVICES
          3.1.1.  Resistors
          3.1.2.  Semiconductor Resistors
          3.1.3.  Semiconductor Resistor Model (R)
          3.1.4.  Capacitors
          3.1.5.  Semiconductor Capacitors
          3.1.6.  Semiconductor Capacitor Model (C)
          3.1.7.  Inductors
          3.1.8.  Coupled (Mutual) Inductors
          3.1.9.  Switches
          3.1.10.  Switch Model (SW/CSW)
        3.2.  VOLTAGE AND CURRENT SOURCES
          3.2.1.  Independent Sources
            3.2.1.1.  Pulse
            3.2.1.2.  Sinusoidal
            3.2.1.3.  Exponential
            3.2.1.4.  Piece-Wise Linear
            3.2.1.5.  Single-Frequency FM
          3.2.2.  Linear Dependent Sources
            3.2.2.1.  Linear Voltage-Controlled Current Sources
            3.2.2.2.  Linear Voltage-Controlled Voltage Sources
            3.2.2.3.  Linear Current-Controlled Current Sources
            3.2.2.4.  Linear Current-Controlled Voltage Sources
          3.2.3.  Non-linear Dependent Sources
        3.3.  TRANSMISSION LINES
          3.3.1.  Lossless Transmission Lines
          3.3.2.  Lossy Transmission Lines
          3.3.3.  Lossy Transmission Line Model (LTRA)
          3.3.4.  Uniform Distributed RC Lines (Lossy)
          3.3.5.  Uniform Distributed RC Model (URC)
        3.4.  TRANSISTORS AND DIODES
          3.4.1.  Junction Diodes
          3.4.2.  Diode Model (D)
          3.4.3.  Bipolar Junction Transistors (BJTs)
          3.4.4.  BJT Models (NPN/PNP)
          3.4.5.  Junction Field-Effect Transistors (JFETs)
          3.4.6.  JFET Models (NJF/PJF)
          3.4.7.  MOSFETs
          3.4.8.  MOSFET Models (NMOS/PMOS)
          3.4.9.  MESFETs
          3.4.10. MESFET Models (NMF/PMF)
      
      4.  ANALYSES AND OUTPUT CONTROL
        4.1.  SIMULATOR VARIABLES (.OPTIONS)
        4.2.  INITIAL CONDITIONS
          4.2.1.  .NODESET: Specify Initial Node Voltage Guesses
          4.2.2.  .IC: Set Initial Conditions
        4.3.  ANALYSES
          4.3.1.  .AC: Small-Signal AC Analysis
          4.3.2.  .DC: DC Transfer Function
          4.3.3.  .DISTO: Distortion Analysis
          4.3.4.  .NOISE: Noise Analysis
          4.3.5.  .OP: Operating Point Analysis
          4.3.6.  .PZ: Pole-Zero Analysis
          4.3.7.  .SENS: DC or Small-Signal AC Sensitivity Analysis
          4.3.8.  .TF: Transfer Function Analysis
          4.3.9.  .TRAN: Transient Analysis
        4.4.  BATCH OUTPUT
          4.4.1.  .SAVE Lines
          4.4.2.  .PRINT Lines
          4.4.3.  .PLOT Lines
          4.4.4.  .FOUR: Fourier Analysis of Transient Analysis Output
      
      5.  INTERACTIVE INTERPRETER
      <mainly snipped: now in 'Interpreter' helpfile>
        5.6.  MISCELLANEOUS
      
      6.  BIBLIOGRAPHY
      
      =============================================================================
      
      
      0. RELEASE NOTES
      
      Spice3f is the six major release of Spice3. This release incorporates new
      features not available in Spice 3c or 3d, as well as several performance
      improvements. All of the features described here are believed to be fully
      functional. The development of SPICE and its algorithms is ongoing at
      Berkeley, and therefore not all of the intended capabilities of the program
      have been implemented in full yet.
      
      Bugs in 3f2 fixed in 3f3:
      
      Ascii (printer) plots in spice3f2 did not print bode plots vs log of the
      frequency by default, as in spice2. You had to explicity request the x-axis
      to be log; either "plot vdb(2) xlog" (best) or "plot vdb(2) vs
      log10(frequency)" will do. Now simply "plot vdb(2)" will work.
      
      The on-line documentation has been brought up to date by converting this
      manual into a format readable on-line.
      
      Significant problems with AC sensitivities in 3f2 only have been fixed.
      Multiple analyses and plots in spice2 emulation mode under 3f2 and earlier
      generated misleading error messages. This no longer happens in 3f3.
      
      New features and bug fixes incorporated in Spice3f (the current release of
      Spice3):
      
      Sensitivity analysis. Added a parameter for fitting JFET models (parameter
      "B"). Fixed a discontinuity problem in MOS level 3
      
      (related to the "kappa" parameter). Working "alter" command. Improved "show"
      and "showmod" commands for operating
      
      point summary tables (like Spice2). Working "trace" command. Interactive
      "set" variable values now the same as ".options" settings. Improved plotting,
      including implicitly transforming data for smith plots. Added the function
      "deriv( )" (derivative) to the front-end. Corrected an error affecting the
      specified initial conditions for
      
      some circuits. Small signal behaviour of non-linear dependant sources fixed.
      Miscellaneous bug fixes in the front end.
      
      New features and bug fixes incorporated in Spice3e (the previous release of
      Spice3):
      
      Lossy Transmission Lines. Proper calculation of sheet resistance in the MOS
      models. A new command ("where") to aid in debugging troublesome circuits.
      Smith-chart plots working (see the "plot" command). Arbitrary sources in
      subcircuits handled correctly. Arbitrary source reciprocal calculations and
      DC biasing fixed. Minor bug-fixes to the Pole-Zero analysis. Miscellaneous
      bug fixes in the front end.
      
      Some common problems remaining in Spice3f (note that this list is not
      complete):
      
      Models defined within subcircuits are not always handled correctly. If you
      have trouble, move the model definition outside of ".subckt" and ".ends"
      lines.
      
      Spice3 User's Manual Batch run data is not compacted if a "rawspice" data
      file is generated, resulting in excessively large output files for some
      difficult inputs.
      
      Sufficient detail is sometimes not preserved in transient analysis. Providing
      a small value for the "TMAX" parameter (the fourth argument) in the transient
      run command will solve this problem.
      
      Convergence problems can sometimes be worked around by relaxing the transient
      "TMAX" parameter.
      
      The substrate node of the bipolar transistor (BJT) is modelled incorrectly
      (this may actually be due to inherant numerical problems with the model). Do
      not use the substrate node; use a semiconductor capacitor to model substrate
      effects.
      
      Charge is not conserved in MOS devices based on the Meyer model. Transient
      simulation of strictly resistive circuits (typical for first runs or tests)
      allow a time step that is too large (e.g. a sinusoidal source driving a
      resistor). There is no integration error to restrict the time step. Use the
      "TMAX" parameter or include reactive elements.
      
      Deep nesting of subcircuits may exceed internal static buffers. The PZ
      analysis can not be interrupted; the sensitivity analysis can not be
      continued (the interactive "resume" command) once interrupted.
      
      There are many other small bugs, particularly in the front end. Bug
      reporting: Please send bug reports or suggested enhancements to Spice3 via
      electronic mail to:
      
      spice@Berkeley.EDU (Internet) ucbvax!spice (UUCP-net)
      
      or by physical mail to "Spice3 Bug Report" at:
      
      EECS/ERL Industrial Support Office 205 Cory Hall U.C. Berkeley Berkeley, CA
      94720
      
      Information on ordering Spice3 or other software distributed through the
      EECS/ERL Industrial Support Office should be directed to the above physical
      mail address or to "ilpsoftware@berkeley.edu" via electronic mail.
      
      Include the version of Spice used, the system type and operating system
      version, the smallest input file demonstrating the problem, and the resulting
      (incorrect) output.
      
      =============================================================================
      
      
      1. INTRODUCTION
      
      SPICE is a general-purpose circuit simulation program for nonlinear dc,
      nonlinear transient, and linear ac analyses. Circuits may contain resistors,
      capacitors, inductors, mutual inductors, independent voltage and current
      sources, four types of dependent sources, lossless and lossy transmission
      lines (two separate implementations), switches, uniform distributed RC lines,
      and the five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs,
      and MOSFETs.
      
      The SPICE3 version is based directly on SPICE 2G.6. While SPICE3 is being
      developed to include new features, it continues to support those capabilities
      and models which remain in extensive use in the SPICE2 program.
      
      SPICE has built-in models for the semiconductor devices, and the user need
      specify only the pertinent model parameter values. The model for the BJT is
      based on the integral-charge model of Gummel and Poon; however, if the
      Gummel- Poon parameters are not specified, the model reduces to the simpler
      Ebers-Moll model. In either case, charge-storage effects, ohmic resistances,
      and a current-dependent output conductance may be included. The diode model
      can be used for either junction diodes or Schottky barrier diodes. The JFET
      model is based on the FET model of Shichman and Hodges. Six MOSFET models are
      implemented: MOS1 is described by a square-law I-V characteristic, MOS2 [1]
      is an analytical model, while MOS3 [1] is a semi-empirical model; MOS6 [2] is
      a simple analytic model accurate in the shortchannel region; MOS4 [3, 4] and
      MOS5 [5] are the BSIM (Berkeley Short-channel IGFET Model) and BSIM2. MOS2,
      MOS3, and MOS4 include second-order effects such as channel-length
      modulation, subthreshold conduction, scattering-limited velocity saturation,
      small-size effects, and charge-controlled capacitances.
      
      
      1.1. TYPES OF ANALYSIS
      
      1.1.1. DC Analysis
      
      The dc analysis portion of SPICE determines the dc operating point of the
      circuit with inductors shorted and capacitors opened. The dc analysis options
      are specified on the .DC, .TF, and .OP control lines. A dc analysis is
      automatically performed prior to a transient analysis to determine the
      transient initial conditions, and prior to an ac small-signal analysis to
      determine the linearized, small-signal models for nonlinear devices. If
      requested, the dc small-signal value of a transfer function (ratio of output
      variable to input source), input resistance, and output resistance is also
      computed as a part of the dc solution. The dc analysis can also be used to
      generate dc transfer curves: a specified independent voltage or current
      source is stepped over a user-specified range and the dc output variables are
      stored for each sequential source value.
      
      
      1.1.2. AC Small-Signal Analysis
      
      The ac small-signal portion of SPICE computes the ac output variables as a
      function of frequency. The program first computes the dc operating point of
      the circuit and determines linearized, small-signal models for all of the
      nonlinear devices in the circuit. The resultant linear circuit is then
      analyzed over a user-specified range of frequencies. The desired output of an
      ac small- signal analysis is usually a transfer function (voltage gain,
      transimpedance, etc). If the circuit has only one ac input, it is convenient
      to set that input to unity and zero phase, so that output variables have the
      same value as the transfer function of the output variable with respect to
      the input.
      
      
      1.1.3. Transient Analysis
      
      The transient analysis portion of SPICE computes the transient output
      variables as a function of time over a user-specified time interval. The
      initial conditions are automatically determined by a dc analysis. All sources
      which are not time dependent (for example, power supplies) are set to their
      dc value. The transient time interval is specified on a .TRAN control line.
      
      1.1.4. Pole-Zero Analysis
      
      The pole-zero analysis portion of SPICE computes the poles and/or zeros in
      the small-signal ac transfer function. The program first computes the dc
      operating point and then determines the linearized, small-signal models for
      all the nonlinear devices in the circuit. This circuit is then used to find
      the poles and zeros of the transfer function.
      
      Two types of transfer functions are allowed : one of the form (output
      voltage)/(input voltage) and the other of the form (output voltage)/(input
      current). These two types of transfer functions cover all the cases and one
      can find the poles/zeros of functions like input/output impedance and voltage
      gain. The input and output ports are specified as two pairs of nodes.
      
      The pole-zero analysis works with resistors, capacitors, inductors,
      linear-controlled sources, independent sources, BJTs, MOSFETs, JFETs and
      diodes. Transmission lines are not supported.
      
      The method used in the analysis is a sub-optimal numerical search. For large
      circuits it may take a considerable time or fail to find all poles and zeros.
      For some circuits, the method becomes "lost" and finds an excessive number of
      poles or zeros.
      
      1.1.5. Small-Signal Distortion Analysis
      
      The distortion analysis portion of SPICE computes steady-state harmonic and
      intermodulation products for small input signal magnitudes. If signals of a
      single frequency are specified as the input to the circuit, the complex
      values of the second and third harmonics are determined at every point in the
      circuit. If there are signals of two frequencies input to the circuit, the
      analysis finds out the complex values of the circuit variables at the sum and
      difference of the input frequencies, and at the difference of the smaller
      frequency from the second harmonic of the larger frequency.
      
      Distortion analysis is supported for the following nonlinear devices: diodes
      (DIO), BJT, JFET, MOSFETs (levels 1, 2, 3, 4/BSIM1, 5/BSIM2, and 6) and
      MESFETS. All linear devices are automatically supported by distortion
      analysis. If there are switches present in the circuit, the analysis
      continues to be accurate provided the switches do not change state under the
      small excitations used for distortion calculations.
      
      
      1.1.6. Sensitivity Analysis
      
      Spice3 will calculate either the DC operating-point sensitivity or the AC
      small-signal sensitivity of an output variable with respect to all circuit
      variables, including model parameters. Spice calculates the difference in an
      output variable (either a node voltage or a branch current) by perturbing
      each parameter of each device independently. Since the method is a numerical
      approximation, the results may demonstrate second order affects in highly
      sensitive parameters, or may fail to show very low but non-zero sensitivity.
      Further, since each variable is perturb by a small fraction of its value,
      zero-valued parameters are not analyized (this has the benefit of reducing
      what is usually a very large amount of data).
      
      
      1.1.7. Noise Analysis
      
      The noise analysis portion of SPICE does analysis device-generated noise for
      the given circuit. When provided with an input source and an output port, the
      analysis calculates the noise contributions of each device (and each noise
      generator within the device) to the output port voltage. It also calculates
      the input noise to the circuit, equivalent to the output noise referred to
      the specified input source. This is done for every frequency point in a
      specified range - the calculated value of the noise corresponds to the
      spectral density of the circuit variable viewed as a stationary gaussian
      stochastic process.
      
      After calculating the spectral densities, noise analysis integrates these
      values over the specified frequency range to arrive at the total noise
      voltage/current (over this frequency range). This calculated value
      corresponds to the variance of the circuit variable viewed as a stationary
      gaussian process.
      
      
      
      1.2. ANALYSIS AT DIFFERENT TEMPERATURES
      
      All input data for SPICE is assumed to have been measured at a nominal
      temperature of 27oC, which can be changed by use of the TNOM parameter on the
      .OPTION control line. This value can further be overridden for any device
      which models temperature effects by specifying the TNOM parameter on the
      model itself. The circuit simulation is performed at a temperature of 27oC,
      unless overridden by a TEMP parameter on the .OPTION control line. Individual
      instances may further override the circuit temperature through the
      specification of a TEMP parameter on the instance.
      
      Temperature dependent support is provided for resistors, diodes, JFETs, BJTs,
      and level 1, 2, and 3 MOSFETs. BSIM (levels 4 and 5) MOSFETs have an
      alternate temperature dependency scheme which adjusts all of the model
      parameters before input to SPICE. For details of the BSIM temperature
      adjustment, see [6] and [7].
      
      Temperature appears explicitly in the exponential terms of the BJT and diode
      model equations. In addition, saturation currents have a built-in temperature
      dependence. The temperature dependence of the saturation current in the BJT
      models is determined by:
                                               ( Es  q  T1  T0 )
      Is  T1 = Is  T0  (T1 / T0) ^ XTI  exp( ---------------- )
                                               (   k  (T1 - T0)  )
      
      where k is Boltzmann's constant, q is the electronic charge, EG is the energy
      gap which is a model parameter, and XTI is the saturation current temperature
      exponent (also a model parameter, and usually equal to 3).
      
      The temperature dependence of forward and reverse beta is according to the
      formula:
      
      (T1) = (T0)  (T1 / T0) ^ XTB
      
      where T1 and T0 are in degrees Kelvin, and XTB is a user-supplied model
      parameter. Temperature effects on beta are carried out by appropriate
      adjustment to the values of bF, ISE, bR, and ISC (spice model parameters BF,
      ISE, BR, and ISC, respectively).
      
      Temperature dependence of the saturation current in the junction diode model
      is determined by:
      
                                                   ( Es  q  T1  T0  )
      Is  T1 = Is  T0  (T1 / T0)^(XTI / N)  exp( ----------------- )
                                                   ( N  k  (T1 - T0) )
      
      where N is the emission coefficient, which is a model parameter, and the
      other symbols have the same meaning as above. Note that for Schottky barrier
      diodes, the value of the saturation current temperature exponent, XTI, is
      usually 2.
      
      Temperature appears explicitly in the value of junction potential, f (in
      spice PHI), for all the device models. The temperature dependence is
      determined by:
      
               k T    ( Na Nd )
      phi(T) = --- ln ( ----- )
                q     ( Ni T )
      
      where k is Boltzmann's constant, q is the electronic charge, Na is the
      acceptor impurity density, Nd is the donor impurity density, Ni is the
      intrinsic carrier concentration, and Eg is the energy gap.
      
      Temperature appears explicitly in the value of surface mobility, u0 (or UO),
      for the MOSFET model. The temperature dependence is determined by:
      
                 0 T0
      0(T) = ------------
              (T / T0)^1.5
      
      The effects of temperature on resistors is modeled by the formula:
      
      R(T) = R(T0) [1 + TC1 (T - T0) + TC2 (T - T0)]
      
      where T is the circuit temperature, T0 is the nominal temperature, and TC1
      and TC2 are the first- and second-order temperature coefficients.
      
      
      1.3. CONVERGENCE
      
      Both dc and transient solutions are obtained by an iterative process which is
      terminated when both of the following conditions hold:
      
      1) The nonlinear branch currents converge to within a tolerance of 0.1% or 1
      picoamp (1.0e-12 Amp), whichever is larger.
      
      2) The node voltages converge to within a tolerance of 0.1% or 1 microvolt
      (1.0e-6 Volt), whichever is larger.
      
      Although the algorithm used in SPICE has been found to be very reliable, in
      some cases it fails to converge to a solution. When this failure occurs, the
      program terminates the job.
      
      Failure to converge in dc analysis is usually due to an error in specifying
      circuit connections, element values, or model parameter values. Regenerative
      switching circuits or circuits with positive feedback probably will not
      converge in the dc analysis unless the OFF option is used for some of the
      devices in the feedback path, or the .NODESET control line is used to force
      the circuit to converge to the desired state.
      
      
      
      2. CIRCUIT DESCRIPTION
      
      2.1. GENERAL STRUCTURE AND CONVENTIONS
      
      The circuit to be analyzed is described to SPICE by a set of element lines,
      which define the circuit topology and element values, and a set of control
      lines, which define the model parameters and the run controls. The first line
      in the input file must be the title, and the last line must be ".END". The
      order of the remaining lines is arbitrary (except, of course, that
      continuation lines must immediately follow the line being continued).
      
      Each element in the circuit is specified by an element line that contains the
      element name, the circuit nodes to which the element is connected, and the
      values of the parameters that determine the electrical characteristics of the
      element. The first letter of the element name specifies the element type. The
      format for the SPICE element types is given in what follows. The strings
      XXXXXXX, YYYYYYY, and ZZZZZZZ denote arbitrary alphanumeric strings. For
      example, a resistor name must begin with the letter R and can contain one or
      more characters. Hence, R, R1, RSE, ROUT, and R3AC2ZY are valid resistor
      names. Details of each type of device are supplied in a following section.
      
      Fields on a line are separated by one or more blanks, a comma, an equal ('=')
      sign, or a left or right parenthesis; extra spaces are ignored. A line may be
      continued by entering a '+' (plus) in column 1 of the following line; SPICE
      continues reading beginning with column 2.
      
      A name field must begin with a letter (A through Z) and cannot contain any
      delimiters.
      
      A number field may be an integer field (12, -44), a floating point field
      (3.14159), either an integer or floating point number followed by an integer
      exponent (1e-14, 2.65e3), or either an integer or a floating point number
      followed by one of the following scale factors:
      
      	T = 1012   G = 109   Meg = 106   K = 103   mil = 25.4-6
      
      	m = 10-3   U (or u) = 10-6n = 10-9   p = 10-12   f = 10-15
      
      Letters immediately following a number that are not scale factors are
      ignored, and letters immediately following a scale factor are ignored. Hence,
      10, 10V, 10Volts, and 10Hz all represent the same number, and M, MA, MSec,
      and MMhos all represent the same scale factor. Note that 1000, 1000.0,
      1000Hz, 1e3, 1.0e3, 1KHz, and 1K all represent the same number.
      
      Nodes names may be arbitrary character strings. The datum (ground) node must
      be named '0'. Note the difference in SPICE3 where the nodes are treated as
      character strings and not evaluated as numbers, thus '0' and '00' are
      distinct nodes in SPICE3 but not in SPICE2. The circuit cannot contain a loop
      of voltage sources and/or inductors and cannot contain a cut-set of current
      sources and/or capacitors. Each node in the circuit must have a dc path to
      ground. Every node must have at least two connections except for transmission
      line nodes (to permit unterminated transmission lines) and MOSFET substrate
      nodes (which have two internal connections anyway).
      
      
      2.2. TITLE LINE, COMMENT LINES AND .END LINE
      
      2.2.1. Title Line Examples:
      
      POWER AMPLIFIER CIRCUIT TEST OF CAM CELL
      
      The title line must be the first in the input file. Its contents are printed
      verbatim as the heading for each section of output.
      
      
      2.2.2. .END Line
      
      Examples:
      
      	.END
      
      The "End" line must always be the last in the input file. Note that the
      period is an integral part of the name.
      
      
      2.2.3. Comments
      
      General Form:
      
      	* <any comment>
      
      Examples:
      
      	* RF=1K Gain should be 100
      	* Check open-loop gain and phase margin
      
      The asterisk in the first column indicates that this line is a comment line.
      Comment lines may be placed anywhere in the circuit description. Note that
      SPICE3 also considers any line with leading white space to be a comment.
      
      
      
      2.3. DEVICE MODELS
      
      General form:
      
      	.MODEL MNAME TYPE(PNAME1=PVAL1 PNAME2=PVAL2 ... )
      
      Examples:
      
      	.MODEL MOD1 NPN (BF=50 IS=1E-13 VBF=50)
      
      Most simple circuit elements typically require only a few parameter values.
      However, some devices (semiconductor devices in particular) that are included
      in SPICE require many parameter values. Often, many devices in a circuit are
      defined by the same set of device model parameters. For these reasons, a set
      of device model parameters is defined on a separate .MODEL line and assigned
      a unique model name. The device element lines in SPICE then refer to the
      model name.
      
      For these more complex device types, each device element line contains the
      device name, the nodes to which the device is connected, and the device model
      name. In addition, other optional parameters may be specified for some
      devices: geometric factors and an initial condition (see the following
      section on Transistors and Diodes for more details).
      
      MNAME in the above is the model name, and type is one of the following
      fifteen types:
      
      R Semiconductor resistor model
      C Semiconductor capacitor model
      SW Voltage controlled switch
      CSW Current controlled switch
      URC Uniform distributed RC model
      LTRA Lossy transmission line model
      D Diode model 
      NPN NPN BJT model 
      PNP PNP BJT model 
      NJF N-channel JFET model 
      PJF P-channel JFET model 
      NMOS N-channel MOSFET model 
      PMOS P-channel MOSFET model 
      NMF N-channel MESFET model
      PMF P-channel MESFET model
      
      Parameter values are defined by appending the parameter name followed by an
      equal sign and the parameter value. Model parameters that are not given a
      value are assigned the default values given below for each model type.
      Models, model parameters, and default values are listed in the next section
      along with the description of device element lines.
      
      
      
      2.4. SUBCIRCUITS
      
      A subcircuit that consists of SPICE elements can be defined and referenced in
      a fashion similar to device models. The subcircuit is defined in the input
      file by a grouping of element lines; the program then automatically inserts
      the group of elements wherever the subcircuit is referenced. There is no
      limit on the size or complexity of subcircuits, and subcircuits may contain
      other subcircuits. An example of subcircuit usage is given in Appendix A.
      
      
      2.4.1. .SUBCKT Line
      
      General form:
      
      	.SUBCKT subnam N1 <N2 N3 ...>
      
      Examples:
      
      	.SUBCKT OPAMP 1 2 3 4
      
      A circuit definition is begun with a .SUBCKT line. SUBNAM is the subcircuit
      name, and N1, N2, ... are the external nodes, which cannot be zero. The group
      of element lines which immediately follow the .SUBCKT line define the
      subcircuit. The last line in a subcircuit definition is the .ENDS line (see
      below). Control lines may not appear within a subcircuit definition; however,
      subcircuit definitions may contain anything else, including other subcircuit
      definitions, device models, and subcircuit calls (see below). Note that any
      device models or subcircuit definitions included as part of a subcircuit
      definition are strictly local (i.e., such models and definitions are not
      known outside the subcircuit definition). Also, any element nodes not
      included on the .SUBCKT line are strictly local, with the exception of 0
      (ground) which is always global.
      
      
      2.4.2. .ENDS Line
      
      General form:
      
      	.ENDS <SUBNAM>
      
      Examples:
      
      	.ENDS OPAMP
      
      The "Ends" line must be the last one for any subcircuit definition. The
      subcircuit name, if included, indicates which subcircuit definition is being
      terminated; if omitted, all subcircuits being defined are terminated. The
      name is needed only when nested subcircuit definitions are being made.
      
      
      2.4.3. Subcircuit Calls
      
      General form:
      
      	XYYYYYYY N1 <N2 N3 ...> SUBNAM
      
      Examples:
      
      	X1 2 4 17 3 1 MULTI
      
      Subcircuits are used in SPICE by specifying pseudo-elements beginning with
      the letter X, followed by the circuit nodes to be used in expanding the
      subcircuit.
      
      
      
      2.5. COMBINING FILES: .INCLUDE LINES
      
      General form:
      
      	.INCLUDE filename
      
      Examples:
      
      	.INCLUDE /users/spice/common/wattmeter.cir
      
      Frequently, portions of circuit descriptions will be reused in several input
      files, particularly with common models and subcircuits. In any spice input
      file, the ".include" line may be used to copy some other file as if that
      second file appeared in place of the ".include" line in the original file.
      There is no restriction on the file name imposed by spice beyond those
      imposed by the local operating system.
      
      
      
      3. CIRCUIT ELEMENTS AND MODELS
      
      Data fields that are enclosed in less-than and greater-than signs ('< >') are
      optional. All indicated punctuation (parentheses, equal signs, etc.) is
      optional but indicate the presence of any delimiter. Further, future
      implementations may require the punctuation as stated. A consistent style
      adhering to the punctuation shown here makes the input easier to understand.
      With respect to branch voltages and currents, SPICE uniformly uses the
      associated reference convention (current flows in the direction of voltage
      drop).
      
      
      3.1. ELEMENTARY DEVICES
      
      3.1.1. Resistors
      
      General form:
      
      	RXXXXXXX N1 N2 VALUE
      
      Examples:
      
      	R1 1 2 100
      	RC1 12 17 1K
      
      N1 and N2 are the two element nodes. VALUE is the resistance (in ohms) and
      may be positive or negative but not zero.
      
      
      3.1.2. Semiconductor Resistors
      
      General form:
      
      	RXXXXXXX N1 N2 <VALUE> <MNAME> <L=LENGTH> <W=WIDTH> <TEMP=T>
      
      Examples:
      
      	RLOAD 2 10 10K
      	RMOD 3 7 RMODEL L=10u W=1u
      
      This is the more general form of the resistor presented in section 6.1, and
      allows the modeling of temperature effects and for the calculation of the
      actual resistance value from strictly geometric information and the
      specifications of the process. If VALUE is specified, it overrides the
      geometric information and defines the resistance. If MNAME is specified, then
      the resistance may be calculated from the process information in the model
      MNAME and the given LENGTH and WIDTH. If VALUE is not specified, then MNAME
      and LENGTH must be specified. If WIDTH is not specified, then it is taken
      from the default width given in the model. The (optional) TEMP value is the
      temperature at which this device is to operate, and overrides the temperature
      specification on the .OPTION control line.
      
      
      3.1.3. Semiconductor Resistor Model (R)
      
      The resistor model consists of process-related device data that allow the
      resistance to be calculated from geometric information and to be corrected
      for temperature. The parameters available are:
      
      name	parameter			units	      default	example
      -------------------------------------------------------------------------------
      TC1	first order temperature coeff.	Ohm/C		0.0	-
      TC2	second order temperature coeff.	Ohm/C		0.0	-
      RSH	sheet resistance		Ohm/square	-	50
      DEFW	default width			meters		1e-6	2e-6
      NARROW	narrowing due to side etching	meters		0.0	1e-7
      TNOM	parameter measurement temp	C		27	50
      
      
      The sheet resistance is used with the narrowing parameter and L and W from
      the resistor device to determine the nominal resistance by the formula
      
      	        (L - NARROW)
      	R = RSH ------------
      	        (W - NARROW) 
      
      DEFW is used to supply a default value for W if one is not specified for the
      device. If either RSH or L is not specified, then the standard default
      resistance value of 1k Ohms  is used. TNOM is used to override the
      circuit-wide value given on the .OPTIONS control line where the parameters of
      this model have been measured at a different temperature. After the nominal
      resistance is calculated, it is adjusted for temperature by the formula:
      
                                                         
      	R(T) = R(T ) [ 1 + TC1 (T - T ) + TC2 (T - T ) ]
                        0                  0              0
      
      
      3.1.4. Capacitors
      
      General form:
      
      	CXXXXXXX N+ N- VALUE <IC=INCOND>
      
      Examples:
      
      	CBYP 13 0 1UF
      	COSC 17 23 10U IC=3V
      
      N+ and N- are the positive and negative element nodes, respectively. VALUE is
      the capacitance in Farads.
      
      The (optional) initial condition is the initial (time-zero) value of
      capacitor voltage (in Volts). Note that the initial conditions (if any) apply
      'only' if the UIC option is specified on the .TRAN control line.
      
      
      3.1.5. Semiconductor Capacitors
      
      General form:
      
      	CXXXXXXX N1 N2 <VALUE> <MNAME> <L=LENGTH> <W=WIDTH> <IC=VAL>
      
      Examples:
      
      	CLOAD 2 10 10P
      	CMOD 3 7 CMODEL L=10u W=1u
      
      This is the more general form of the Capacitor presented in section 6.2, and
      allows for the calculation of the actual capacitance value from strictly
      geometric information and the specifications of the process. If VALUE is
      specified, it defines the capacitance. If MNAME is specified, then the
      capacitance is calculated from the process information in the model MNAME and
      the given LENGTH and WIDTH. If VALUE is not specified, then MNAME and LENGTH
      must be specified. If WIDTH is not specified, then it is taken from the
      default width given in the model. Either VALUE or MNAME, LENGTH, and WIDTH
      may be specified, but not both sets.
      
      
      
      3.1.6. Semiconductor Capacitor Model (C)
      
      The capacitor model contains process information that may be used to compute
      the capacitance from strictly geometric information.
      
      name 	parameter 			units 		default example
      -----------------------------------------------------------------------
      CJ 	junction bottom capacitance 	F/meters	 -	5e-5
      CJSW 	junction sidewall capacitance 	F/meters	 -	2e-11
      DEFW 	default	device width 		meters	 	1e-6	2e-6
      NARROW 	narrowing due to side etching 	meters	 	0.0	1e-7
      
      
      The capacitor has a capacitance computed as
      
      CAP = CJ (LENGTH - NARROW) (WIDTH - NARROW) + 2 CJSW (LENGTH + WIDTH - 2 NARROW)
      
      
      
      3.1.7. Inductors
      
      General form:
      
      	LYYYYYYY N+ N- VALUE <IC=INCOND>
      
      Examples:
      
      	LLINK 42 69 1UH
      	LSHUNT 23 51 10U IC=15.7MA
      
      N+ and N- are the positive and negative element nodes, respectively. VALUE is
      the inductance in Henries.
      
      The (optional) initial condition is the initial (time-zero) value of inductor
      current (in Amps) that flows from N+, through the inductor, to N-. Note that
      the initial conditions (if any) apply only if the UIC option is specified on
      the .TRAN analysis line.
      
      
      
      3.1.8. Coupled (Mutual) Inductors
      
      General form:
      
      	KXXXXXXX LYYYYYYY LZZZZZZZ VALUE
      
      Examples:
      
      	K43 LAA LBB 0.999 KXFRMR L1 L2 0.87
      
      LYYYYYYY and LZZZZZZZ are the names of the two coupled inductors, and VALUE
      is the coefficient of coupling, K, which must be greater than 0 and less than
      or equal to 1. Using the 'dot' convention, place a 'dot' on the first node of
      each inductor.
      
      
      3.1.9. Switches
      
      General form:
      
      	SXXXXXXX N+ N- NC+ NC- MODEL <ON><OFF>
      	WYYYYYYY N+ N- VNAM MODEL <ON><OFF>
      
      Examples:
      
      	s1 1 2 3 4 switch1 ON
      	s2 5 6 3 0 sm2 off
      	Switch1 1 2 10 0 smodel1
      	w1 1 2 vclock switchmod1
      	W2 3 0 vramp sm1 ON
      	wreset 5 6 vclck lossyswitch OFF
      
      Nodes 1 and 2 are the nodes between which the switch terminals are connected.
      The model name is mandatory while the initial conditions are optional. For
      the voltage controlled switch, nodes 3 and 4 are the positive and negative
      controlling nodes respectively. For the current controlled switch, the
      controlling current is that through the specified voltage source. The
      direction of positive controlling current flow is from the positive node,
      through the source, to the negative node.
      
      
      3.1.10. Switch Model (SW/CSW)
      
      The switch model allows an almost ideal switch to be described in SPICE. The
      switch is not quite ideal, in that the resistance can not change from 0 to
      infinity, but must always have a finite positive value. By proper selection
      of the on and off resistances, they can be effectively zero and infinity in
      comparison to other circuit elements. The parameters available are:
      
      name	parameter		units	default		switch
      ---------------------------------------------------------------
      VT	threshold voltage 	Volts 	0.0 		S
      IT	threshold current 	Amps 	0.0 		W
      VH	hysteresis voltage 	Volts 	0.0 		S
      IH 	hysteresis current 	Amps 	0.0 		W
      RON 	on resistance		Ohms	1.0 		both
      ROFF	off resistance		Ohms	1/GMIN*		both
      
      *(See the .OPTIONS control line for a description of GMIN, its default value
      results in an offresistance of 1.0e+12 ohms.)
      
      The use of an ideal element that is highly nonlinear such as a switch can
      cause large discontinuities to occur in the circuit node voltages. A rapid
      change such as that associated with a switch changing state can cause
      numerical roundoff or tolerance problems leading to erroneous results or
      timestep difficulties. The user of switches can improve the situation by
      taking the following steps:
      
      First, it is wise to set ideal switch impedances just high or low enough to
      be negligible with respect to other circuit elements. Using switch impedances
      that are close to "ideal" in all cases aggravates the problem of
      discontinuities mentioned above. Of course, when modeling real devices such
      as MOSFETS, the on resistance should be adjusted to a realistic level
      depending on the size of the device being modeled.
      
      If a wide range of ON to OFF resistance must be used in the switches
      (ROFF/RON >1e+12), then the tolerance on errors allowed during transient
      analysis should be decreased by using the .OPTIONS control line and
      specifying TRTOL to be less than the default value of 7.0. When switches are
      placed around capacitors, then the option CHGTOL should also be reduced.
      Suggested values for these two options are 1.0 and 1e-16 respectively. These
      changes inform SPICE3 to be more careful around the switch points so that no
      errors are made due to the rapid change in the circuit.
      
      
      
      3.2. VOLTAGE AND CURRENT SOURCES
      
      3.2.1. Independent Sources
      
      General form:
      
      	VXXXXXXX N+ N- <<DC> DC/TRAN VALUE> <AC <ACMAG <ACPHASE>>>
      	+ <DISTOF1 <F1MAG <F1PHASE>>> <DISTOF2 <F2MAG <F2PHASE>>>
      
      	IYYYYYYY N+ N- <<DC> DC/TRAN VALUE> <AC <ACMAG <ACPHASE>>>
      	+ <DISTOF1 <F1MAG <F1PHASE>>> <DISTOF2 <F2MAG <F2PHASE>>>
      
      Examples:
      
      	VCC 10 0 DC 6
      	VIN 13 2 0.001 AC 1 SIN(0 1 1MEG)
      	ISRC 23 21 AC 0.333 45.0 SFFM(0 1 10K 5 1K)
      	VMEAS 12 9
      	VCARRIER 1 0 DISTOF1 0.1 -90.0
      	VMODULATOR 2 0 DISTOF2 0.01
      	IIN1 1 5 AC 1 DISTOF1 DISTOF2 0.001
      
      N+ and N- are the positive and negative nodes, respectively. Note that
      voltage sources need not be grounded. Positive current is assumed to flow
      from the positive node, through the source, to the negative node. A current
      source of positive value forces current to flow out of the N+ node, through
      the source, and into the N- node. Voltage sources, in addition to being used
      for circuit excitation, are the 'ammeters' for SPICE, that is, zero valued
      voltage sources may be inserted into the circuit for the purpose of measuring
      current. They of course have no effect on circuit operation since they
      represent short-circuits.
      
      DC/TRAN is the dc and transient analysis value of the source. If the source
      value is zero both for dc and transient analyses, this value may be omitted.
      If the source value is time-invariant (e.g., a power supply), then the value
      may optionally be preceded by the letters DC.
      
      ACMAG is the ac magnitude and ACPHASE is the ac phase. The source is set to
      this value in the ac analysis. If ACMAG is omitted following the keyword AC,
      a value of unity is assumed. If ACPHASE is omitted, a value of zero is
      assumed. If the source is not an ac small-signal input, the keyword AC and
      the ac values are omitted.
      
      DISTOF1 and DISTOF2 are the keywords that specify that the independent source
      has distortion inputs at the frequencies F1 and F2 respectively (see the
      description of the .DISTO control line). The keywords may be followed by an
      optional magnitude and phase. The default values of the magnitude and phase
      are 1.0 and 0.0 respectively.
      
      Any independent source can be assigned a time-dependent value for transient
      analysis. If a source is assigned a time-dependent value, the time-zero value
      is used for dc analysis. There are five independent source functions: pulse,
      exponential, sinusoidal, piece-wise linear, and single-frequency FM. If
      parameters other than source values are omitted or set to zero, the default
      values shown are assumed. (TSTEP is
      
      VOLTAGE AND CURRENT SOURCES the printing increment and TSTOP is the final
      time (see the .TRAN control line for explanation)).
      
      
      3.2.1.1. Pulse
      
      General form:
      
      	PULSE(V1 V2 TD TR TF PW PER)
      
      Examples:
      
      	VIN 3 0 PULSE(-1 1 2NS 2NS 2NS 50NS 100NS)
      
      
      parameter		default value	units
      -----------------------------------------------------
      V1 (initial value) 			Volts or Amps
      V2 (pulsed value) 			Volts or Amps
      TD (delay time) 	0.0 		seconds
      TR (rise time) 		TSTEP 		seconds
      TF (fall time)		TSTEP 		seconds
      PW (pulse width) 	TSTOP 		seconds
      PER(period)		TSTOP		seconds
      
      
      A single pulse so specified is described by the following table:
      
      time		value
      ---------------------
      0 		V1
      TD 		V1
      TD+TR 		V2
      TD+TR+PW 	V2
      TD+TR+PW+TF 	V1
      TSTOP 		V1
      
      Intermediate points are determined by linear interpolation.
      
      
      3.2.1.2. Sinusoidal
      
      General form:
      
      	SIN(VO VA FREQ TD THETA)
      
      Examples:
      
      	VIN 3 0 SIN(0 1 100MEG 1NS 1E10)
      
      
      parameters 		default value 	units
      ------------------------------------------------------
      VO (offset) 				Volts or Amps
      VA (amplitude) 				Volts or Amps
      FREQ (frequency) 	1/TSTOP 	Hz
      TD (delay) 		0.0 		seconds
      THETA (damping factor) 	0.0 		1/seconds
      
      
      The shape of the waveform is described by the following table:
      
      time 		value
      ---------------------------------------------------------------
      0 to TD		VO
      TD to TSTOP	VO + VA exp[-(t - TD) THETA] sin(2 pi FREQ (t + TD))
      
      
      3.2.1.3. Exponential
      
      General Form:
      
      	EXP(V1 V2 TD1 TAU1 TD2 TAU2)
      
      Examples:
      
      	VIN 3 0 EXP(-4 -1 2NS 30NS 60NS 40NS)
      
      
      parameter 			default value 	units
      -------------------------------------------------------------
      V1 (initial value) 				Volts or Amps
      V2 (pulsed value) 				Volts or Amps
      TD1 (rise delay time) 		0.0 		seconds
      TAU1 (rise time constant) 	TSTEP 		seconds
      TD2 (fall delay time) 		TD1+TSTEP 	seconds
      TAU2 (fall time constant) 	TSTEP 		seconds
      
      
      The shape of the waveform is described by the following table:
      
      time 		value
      ------------------------------------------------------------
      0 to TD1 	V1
      
      TD1 to TD2 	V1 + (V2 - V1) [ 1 - exp( -(t - TD1) / TAU1) ]
      
      TD2 to TSTOP	V1 + (V2 - V1) [ -exp( -(t - TD1) / TAU1 ]
      		   + (V1 - V2) [ 1 - exp( -(t - TD2) / TAU2) ]
      
      
      
      3.2.1.4. Piece-Wise Linear
      
      General Form:
      
      	PWL(T1 V1 <T2 V2 T3 V3 T4 V4 ...>)
      
      Examples:
      
      	VCLOCK 7 5 PWL(0 -7 10NS -7 11NS -3 17NS -3 18NS -7 50NS -7)
      
      Each pair of values (Ti, Vi) specifies that the value of the source is Vi (in
      Volts or Amps) at time=Ti. The value of the source at intermediate values of
      time is determined by using linear interpolation on the input values.
      
      
      3.2.1.5. Single-Frequency FM
      
      General Form:
      
      	SFFM(VO VA FC MDI FS)
      
      Examples:
      
      	V1 12 0 SFFM(0 1M 20K 5 1K)
      
      parameter 		default value 	units
      ------------------------------------------------------------
      VO (offset) 				Volts or Amps
      VA (amplitude) 				Volts or Amps
      FC (carrier frequency) 	1/TSTOP 	Hz
      MDI (modulation index)
      FS (signal frequency) 	1/TSTOP 	Hz
      
      The shape of the waveform is described by the following equation:
      
      	V(t) = VO + VA sin [ 2 pi FC t + MDI sin(2 pi FS t) ]
      
      
      
      3.2.2. Linear Dependent Sources
      
      SPICE allows circuits to contain linear dependent sources characterized by
      any of the four equations
      
      i = g v		v = e v		i = f i		v = h i
      
      where g, e, f, and h are constants representing transconductance, voltage
      gain, current gain, and transresistance, respectively.
      
      
      
      3.2.2.1. Linear Voltage-Controlled Current Sources
      
      General form:
      
      	GXXXXXXX N+ N- NC+ NC- VALUE
      
      Examples:
      
      	G1 2 0 5 0 0.1MMHO
      
      N+ and N- are the positive and negative nodes, respectively. Current flow is
      from the positive node, through the source, to the negative node. NC+ and NC-
      are the positive and negative controlling nodes, respectively. VALUE is the
      transconductance (in mhos).
      
      
      3.2.2.2. Linear Voltage-Controlled Voltage Sources
      
      General form:
      
      	EXXXXXXX N+ N- NC+ NC- VALUE
      
      Examples:
      
      	E1 2 3 14 1 2.0
      
      N+ is the positive node, and N- is the negative node. NC+ and NC- are the
      positive and negative controlling nodes, respectively. VALUE is the voltage
      gain.
      
      
      
      3.2.2.3. Linear Current-Controlled Current Sources
      
      General form:
      
      	FXXXXXXX N+ N- VNAM VALUE
      
      Examples:
      
      	F1 13 5 VSENS 5
      
      N+ and N- are the positive and negative nodes, respectively. Current flow is
      from the positive node, through the source, to the negative node. VNAM is the
      name of a voltage source through which the controlling current flows. The
      direction of positive controlling current flow is from the positive node,
      through the source, to the negative node of VNAM. VALUE is the current gain.
      
      
      3.2.2.4. Linear Current-Controlled Voltage Sources
      
      General form:
      
      	HXXXXXXX N+ N- VNAM VALUE
      
      Examples:
      
      	HX 5 17 VZ 0.5K
      
      N+ and N- are the positive and negative nodes, respectively. VNAM is the name
      of a voltage source through which the controlling current flows. The
      direction of positive controlling current flow is from the positive node,
      through the source, to the negative node of VNAM. VALUE is the
      transresistance (in ohms).
      
      
      3.2.3. Non-linear Dependent Sources
      
      General form:
      
      	BXXXXXXX N+ N- <I=EXPR> <V=EXPR>
      
      Examples:
      
      	B1 0 1 I=cos(v(1))+sin(v(2))
      	B1 0 1 V=ln(cos(log(v(1,2)^2)))-v(3)^4+v(2)^v(1)
      	B1 3 4 I=17
      	B1 3 4 V=exp(pi^i(vdd))
      
      N+ is the positive node, and N- is the negative node. The values of the V and
      I parameters determine the voltages and currents across and through the
      device, respectively. If I is given then the device is a current source, and
      if V is given the device is a voltage source. One and only one of these
      parameters must be given.
      
      The small-signal AC behavior of the nonlinear source is a linear dependent
      source (or sources) with a proportionality constant equal to the derivative
      (or derivatives) of the source at the DC operating point.
      
      The expressions given for V and I may be any function of voltages and
      currents through voltage sources in the system. The following functions of
      real variables are defined:
      
      	abs 	asinh 	cosh 	sin
      	acos 	atan 	exp 	sinh
      	acosh 	atanh 	ln 	sqrt
      	asin 	cos 	log 	tan
      
      The function "u" is the unit step function, with a value of one for arguments
      greater than one and a value of zero for arguments less than zero. The
      function "uramp" is the integral of the unit step: for an input x, the value
      is zero if x is less than zero, or if x is greater than zero the value is x.
      These two functions are useful in sythesizing piece-wise non-linear
      functions, though convergence may be adversely affected.
      
      The following standard operators are defined:
      
      	+ 	- 	* 	/ 	^ 	unary -
      
      If the argument of log, ln, or sqrt becomes less than zero, the absolute
      value of the argument is used. If a divisor becomes zero or the argument of
      log or ln becomes zero, an error will result. Other problems may occur when
      the argument for a function in a partial derivative enters a region where
      that function is undefined.
      
      To get time into the expression you can integrate the current from a constant
      current source with a capacitor and use the resulting voltage (don't forget
      to set the initial voltage across the capacitor). Nonlinear resistors,
      capacitors, and inductors may be synthesized with the nonlinear dependent
      source. Nonlinear resistors are obvious. Non-linear capacitors and inductors
      are implemented with their linear counterparts by a change of variables
      implemented with the nonlinear dependent source. The following subcircuit
      will implement a nonlinear capacitor:
      
      	.Subckt nlcap pos neg
      	* Bx: calculate f(input voltage)
      	Bx 1 0 v = f(v(pos,neg))
      	* Cx: linear capacitance
      	Cx 2 0 1
      	* Vx: Ammeter to measure current into the capacitor
      	Vx 2 1 DC 0Volts
      	* Drive the current through Cx back into the circuit
      	Fx pos neg Vx 1 .ends
      
      Non-linear inductors are similar.
      
      
      
      3.3. TRANSMISSION LINES
      
      
      3.3.1. Lossless Transmission Lines
      
      General form:
      
      	TXXXXXXX N1 N2 N3 N4 Z0=VALUE <TD=VALUE> <F=FREQ <NL=NRMLEN>>
      	+ <IC=V1, I1, V2, I2>
      
      Examples:
      
      	T1 1 0 2 0 Z0=50 TD=10NS
      
      N1 and N2 are the nodes at port 1; N3 and N4 are the nodes at port 2. Z0 is
      the characteristic impedance. The length of the line may be expressed in
      either of two forms. The transmission delay, TD, may be specified directly
      (as TD=10ns, for example). Alternatively, a frequency F may be given,
      together with NL, the normalized electrical length of the transmission line
      with respect to the wavelength in the line at the frequency F. If a frequency
      is specified but NL is omitted, 0.25 is assumed (that is, the frequency is
      assumed to be the quarter-wave frequency). Note that although both forms for
      expressing the line length are indicated as optional, one of the two must be
      specified.
      
      Note that this element models only one propagating mode. If all four nodes
      are distinct in the actual circuit, then two modes may be excited. To
      simulate such a situation, two transmission-line elements are required. (see
      the example in Appendix A for further clarification.)
      
      The (optional) initial condition specification consists of the voltage and
      current at each of the transmission line ports. Note that the initial
      conditions (if any) apply 'only' if the UIC option is specified on the .TRAN
      control line.
      
      Note that a lossy transmission line (see below) with zero loss may be more
      accurate than than the lossless transmission line due to implementation
      details.
      
      
      
      3.3.2. Lossy Transmission Lines
      
      General form:
      
      	OXXXXXXX N1 N2 N3 N4 MNAME
      
      Examples:
      
      	O23 1 0 2 0 LOSSYMOD OCONNECT 10 5 20 5 INTERCONNECT
      
      This is a two-port convolution model for single-conductor lossy transmission
      lines. N1 and N2 are the nodes at port 1; N3 and N4 are the nodes at port 2.
      Note that a lossy transmission line with zero loss may be more accurate than
      than the lossless transmission line due to implementation details.
      
      
      
      3.3.3. Lossy Transmission Line Model (LTRA)
      
      The uniform RLC/RC/LC/RG transmission line model (referred to as the LTRA
      model henceforth) models a uniform constant-parameter distributed
      transmission line. The RC and LC cases may also be modeled using the URC and
      TRA models; however, the newer LTRA model is usually faster and more accurate
      than the others. The operation of the LTRA model is based on the convolution
      of the transmission line's impulse responses with its inputs (see [8]).
      
      The LTRA model takes a number of parameters, some of which must be given and
      some of which are optional.
      
      name 		parameter 			units/type    default	example
      --------------------------------------------------------------------------------
      R 		resistance/length 		Ohms/unit 	0.0 	 0.2
      L 		inductance/length 		henrys/unit 	0.0 	 9.13e-9
      G 		conductance/length 		mhos/unit 	0.0 	 0.0
      C 		capacitance/length 		farads/unit 	0.0 	 3.65e-12
      LEN 		length of line 					none	 1.0
      REL 		breakpoint control 		arbitrary unit 	1 	 0.5
      ABS 		breakpoint control 				1 	 5
      NOSTEPLIMIT 	don't limit timestep to less	flag		not set	 set
      		than line delay
      NOCONTROL 	don't do complex timestep 	flag 		not set	 set
      		control
      LININTERP 	use linear interpolation 	flag 		not set	 set
      MIXEDINTERP 	use linear when quadratic  			not set	 set
      		seems bad
      COMPACTREL 	special reltol for history 	flag		RELTOL	 1.0e-3
      		compaction
      COMPACTABS 	special abstol for history flag			ABSTOL 	 1.0e-9
      		compaction
      TRUNCNR		use Newton-Raphson method for	flag		not set	 set
      		timestep control
      TRUNCDONTCUT 	don't limit timestep to keep 	flag		not set	 set
      		impulse-response errors low
      
      The following types of lines have been implemented so far: RLC (uniform
      transmission line with series loss only), RC (uniform RC line), LC (lossless
      transmission line), and RG (distributed series resistance and parallel
      conductance only). Any other combination will yield erroneous results and
      should not be tried. The length LEN of the line must be specified.
      
      NOSTEPLIMIT is a flag that will remove the default restriction of limiting
      time-steps to less than the line delay in the RLC case. NOCONTROL is a flag
      that prevents the default limiting of the time-step based on convolution
      error criteria in the RLC and RC cases. This speeds up simulation but may in
      some cases reduce the accuracy of results. LININTERP is a flag that, when
      specified, will use linear interpolation instead of the default quadratic
      interpolation for calculating delayed signals. MIXEDINTERP is a flag that,
      when specified, uses a metric for judging whether quadratic interpolation is
      not applicable and if so uses linear interpolation; otherwise it uses the
      default quadratic interpolation. TRUNCDONTCUT is a flag that removes the
      default cutting of the time-step to limit errors in the actual calculation of
      impulse-response related quantities. COMPACTREL and COMPACTABS are quantities
      that control the compaction of the past history of values stored for
      convolution. Larger values of these lower accuracy but usually increase
      simulation speed. These are to be used with the TRYTOCOMPACT option,
      described in the .OPTIONS section. TRUNCNR is a flag that turns on the use of
      Newton-Raphson iterations to determine an appropriate timestep in the
      timestep control routines. The default is a trial and error procedure by
      cutting the previous timestep in half. REL and ABS are quantities that
      control the setting of breakpoints.
      
      The option most worth experimenting with for increasing the speed of
      simulation is REL. The default value of 1 is usually safe from the point of
      view of accuracy but occasionally increases computation time. A value greater
      than 2 eliminates all breakpoints and may be worth trying depending on the
      nature of the rest of the circuit, keeping in mind that it might not be safe
      from the viewpoint of accuracy. Breakpoints may usually be entirely
      eliminated if it is expected the circuit will not display sharp
      discontinuities. Values between 0 and 1 are usually not required but may be
      used for setting many breakpoints.
      
      COMPACTREL may also be experimented with when the option TRYTOCOMPACT is
      specified in a .OPTIONS card. The legal range is between 0 and 1. Larger
      values usually decrease the accuracy of the simulation but in some cases
      improve speed. If TRYTOCOMPACT is not specified on a .OPTIONS card, history
      compaction is not attempted and accuracy is high. NOCONTROL, TRUNCDONTCUT and
      NOSTEPLIMIT also tend to increase speed at the expense of accuracy.
      
      
      
      3.3.4. Uniform Distributed RC Lines (Lossy)
      
      General form:
      
      	UXXXXXXX N1 N2 N3 MNAME L=LEN <N=LUMPS>
      
      Examples:
      
      	U1 1 2 0 URCMOD L=50U
      	URC2 1 12 2 UMODL l=1MIL N=6
      
      N1 and N2 are the two element nodes the RC line connects, while N3 is the
      node to which the capacitances are connected. MNAME is the model name, LEN is
      the length of the RC line in meters. LUMPS, if specified, is the number of
      lumped segments to use in modeling the RC line (see the model description for
      the action taken if this parameter is omitted).
      
      
      3.3.5. Uniform Distributed RC Model (URC)
      
      The URC model is derived from a model proposed by L. Gertzberrg in 1974. The
      model is accomplished by a subcircuit type expansion of the URC line into a
      network of lumped RC segments with internally generated nodes. The RC
      segments are in a geometric progression, increasing toward the middle of the
      URC line, with K as a proportionality constant. The number of lumped segments
      used, if not specified for the URC line device, is determined by the
      following formula:
      
               |      R C        | K - 1 | |
            log| F    - - 2 J L | ----- |  |
               |  max L L        |   K   |  |
        N = ----------------------------------
                          log K
      
      
      The URC line is made up strictly of resistor and capacitor segments unless
      the ISPERL parameter is given a non-zero value, in which case the capacitors
      are replaced with reverse biased diodes with a zerobias junction capacitance
      equivalent to the capacitance replaced, and with a saturation current of
      ISPERL amps per meter of transmission line and an optional series resistance
      equivalent to RSPERL ohms per meter.
      
      
        name 	 parameter 			units	default	example	area
      -------------------------------------------------------------------------
      1 K 	 Propagation Constant	 	 - 	2.0 	1.2 	-
      2 FMAX 	 Maximum Frequency of interest 	 Hz 	1.0G 	6.5Meg  -
      3 RPERL  Resistance per unit length 	 Ohm/m 	1000 	10 	-
      4 CPERL  Capacitance per unit length 	 F/m 	1.0e-15 1pF	-
      5 ISPERL Saturation Current/unit length	 A/m	0 	- 	-
      6 RSPERL Diode Resistance/unit length	 Ohm/m 	0 	- 	-
      
      
      
      3.4. TRANSISTORS AND DIODES
      
      The area factor used on the diode, BJT, JFET, and MESFET devices determines
      the number of equivalent parallel devices of a specified model. The affected
      parameters are marked with an asterisk under the heading 'area' in the model
      descriptions below. Several geometric factors associated with the channel and
      the drain and source diffusions can be specified on the MOSFET device line.
      
      Two different forms of initial conditions may be specified for some devices.
      The first form is included to improve the dc convergence for circuits that
      contain more than one stable state. If a device is specified OFF, the dc
      operating point is determined with the terminal voltages for that device set
      to zero. After convergence is obtained, the program continues to iterate to
      obtain the exact value for the terminal voltages. If a circuit has more than
      one dc stable state, the OFF option can be used to force the solution to
      correspond to a desired state. If a device is specified OFF when in reality
      the device is conducting, the program still obtains the correct solution
      (assuming the solutions converge) but more iterations are required since the
      program must independently converge to two separate solutions. The .NODESET
      control line serves a similar purpose as the OFF option. The .NODESET option
      is easier to apply and is the preferred means to aid convergence.
      
      The second form of initial conditions are specified for use with the
      transient analysis. These are true 'initial conditions' as opposed to the
      convergence aids above. See the description of the .IC control line and the
      .TRAN control line for a detailed explanation of initial conditions.
      
      
      3.4.1. Junction Diodes
      
      General form:
      
      	DXXXXXXX N+ N- MNAME <AREA> <OFF> <IC=VD> <TEMP=T>
      
      Examples:
      
      	DBRIDGE 2 10 DIODE1
      	DCLMP 3 7 DMOD 3.0 IC=0.2
      
      N+ and N- are the positive and negative nodes, respectively. MNAME is the
      model name, AREA is the area factor, and OFF indicates an (optional) starting
      condition on the device for dc analysis. If the area factor is omitted, a
      value of 1.0 is assumed. The (optional) initial condition specification using
      IC=VD is intended for use with the UIC option on the .TRAN control line, when
      a transient analysis is desired starting from other than the quiescent
      operating point. The (optional) TEMP value is the temperature at which this
      device is to operate, and overrides the temperature specification on the
      .OPTION control line.
      
      
      3.4.2. Diode Model (D)
      
      The dc characteristics of the diode are determined by the parameters IS and
      N. An ohmic resistance, RS, is included. Charge storage effects are modeled
      by a transit time, TT, and a nonlinear depletion layer capacitance which is
      determined by the parameters CJO, VJ, and M. The temperature dependence of
      the saturation current is defined by the parameters EG, the energy and XTI,
      the saturation current temperature exponent. The nominal temperature at which
      these parameters were measured is TNOM, which defaults to the circuit-wide
      value specified on the .OPTIONS control line. Reverse breakdown is modeled by
      an exponential increase in the reverse diode current and is determined by the
      parameters BV and IBV (both of which are positive numbers).
      
         name	parameter 			units	default		example	area
      ------------------------------------------------------------------------------
      1  IS 	saturation current 		A 	1.0e-14		1.0e-14	 *
      2  RS 	ohmic resistance 		Ohm  	0 		10 	 *
      3  N 	emission coefficient 		- 	1 		1.0
      4  TT 	transit-time 			sec 	0 		0.1ns
      5  CJO 	zero-bias junction capacitance 	F 	0 		2pF	 *
      6  VJ 	junction potential 		V	1 		0.6
      7  M 	grading coefficient 		- 	0.5 		0.5
      8  EG 	activation energy 		eV 	1.11 		1.11 Si
      								0.69 Sbd
      								0.67 Ge
      9  XTI 	saturation-current temp. exp 	- 	3.0 		3.0 jn
      								2.0 Sbd
      10 KF 	flicker noise coefficient 	- 	0
      11 AF 	flicker noise exponent 		- 	1
      12 FC 	coefficient for forward-bias 	- 	0.5
      	depletion capacitance formula
      13 BV 	reverse breakdown voltage 	V 	infinite 	40.0
      14 IBV 	current at breakdown voltage 	A 	1.0e-3
      15 TNOM	parameter measurement temp	C 	27 		50
      
      
      
      3.4.3. Bipolar Junction Transistors (BJTs)
      
      General form:
      
      	QXXXXXXX NC NB NE <NS> MNAME <AREA> <OFF> <IC=VBE, VCE> <TEMP=T>
      
      Examples:
      
      	Q23 10 24 13 QMOD IC=0.6, 5.0
      	Q50A 11 26 4 20 MOD1
      
      NC, NB, and NE are the collector, base, and emitter nodes, respectively. NS
      is the (optional) substrate node. If unspecified, ground is used. MNAME is
      the model name, AREA is the area factor, and OFF indicates an (optional)
      initial condition on the device for the dc analysis. If the area factor is
      omitted, a value of 1.0 is assumed. The (optional) initial condition
      specification using IC=VBE, VCE is intended for use with the UIC option on
      the .TRAN control line, when a transient analysis is desired starting from
      other than the quiescent operating point. See the .IC control line
      description for a better way to set transient initial conditions. The
      (optional) TEMP value is the temperature at which this device is to operate,
      and overrides the temperature specification on the .OPTION control line.
      
      
      3.4.4. BJT Models (NPN/PNP)
      
      The bipolar junction transistor model in SPICE is an adaptation of the
      integral charge control model of Gummel and Poon. This modified Gummel-Poon
      model extends the original model to include several effects at high bias
      levels. The model automatically simplifies to the simpler Ebers-Moll model
      when certain parameters are not specified. The parameter names used in the
      modified Gummel-Poon model have been chosen to be more easily understood by
      the program user, and to reflect better both physical and circuit design
      thinking.
      
      The dc model is defined by the parameters IS, BF, NF, ISE, IKF, and NE which
      determine the forward current gain characteristics, IS, BR, NR, ISC, IKR, and
      NC which determine the reverse current gain characteristics, and VAF and VAR
      which determine the output conductance for forward and reverse regions. Three
      ohmic resistances RB, RC, and RE are included, where RB can be high current
      dependent. Base charge storage is modeled by forward and reverse transit
      times, TF and TR, the forward transit time TF being bias dependent if
      desired, and nonlinear depletion layer capacitances which are determined by
      CJE, VJE, and MJE for the B-E junction , CJC, VJC, and MJC for the B-C
      junction and CJS, VJS, and MJS for the C-S (Collector-Substrate) junction.
      The temperature dependence of the saturation current, IS, is determined by
      the energy-gap, EG, and the saturation current temperature exponent, XTI.
      Additionally base current temperature dependence is modeled by the beta
      temperature exponent XTB in the new model. The values specified are assumed
      to have been measured at the temperature TNOM, which can be specified on the
      .OPTIONS control line or overridden by a specification on the .MODEL line.
      
      The BJT parameters used in the modified Gummel-Poon model are listed below.
      The parameter names used in earlier versions of SPICE2 are still accepted.
      
      Modified Gummel-Poon BJT Parameters.
      
        name	parameter			units	default		example	area
      -------------------------------------------------------------------------------------
      1  IS	transport saturation current 	A 	1.0e-16 	1.0e-15  *
      2  BF 	ideal maximum forward beta 	- 	100 		100
      3  NF 	forward current emission coef. 	- 	1.0 		1
      4  VAF 	forward Early voltage 		V 	infinite 	200
      5  IKF 	corner for forward  high
      	 current roll-off		A 	infinite 	0.01 	 *
      6  ISE 	B-E leakage saturation current 	A 	0 		1.0e-13	 *
      7  NE 	B-E leakage emission coef 	- 	1.5 		2
      8  BR 	ideal maximum reverse beta 	- 	1 		0.1
      9  NR 	reverse current emission coef 	- 	1 		1
      10 VAR 	reverse Early voltage 		V 	infinite 	200
      11 IKR 	corner for reverse beta
      	high current roll-off		A 	infinite 	0.01	 *
      12 ISC 	B-C leakage saturation current 	A 	0 		1.0e-13	 *
      13 NC 	B-C leakage emission coef 	- 	2 		1.5
      14 RB 	zero bias base resistance 	Ohms  	0 		100	 *
      15 IRB 	current where base resistance
      	falls halfway to its min value	A 	infinite 	0.1	 *
      16 RBM 	minimum base resistance at
      	high currents			Ohms	RB 		10	 *
      17 RE 	emitter resistance 		Ohms  	0 		1	 *
      18 RC 	collector resistance 		Ohms  	0 		10	 *
      19 CJE 	B-E zero-bias depletion
      	capacitance		 	F 	0 		2pF	 *
      20 VJE 	B-E built-in potential 		V 	0.75 		0.6
      21 MJE 	B-E junction exponential factor	- 	0.33 		0.33
      22 TF 	ideal forward transit time 	sec 	0 		0.1ns
      23 XTF 	coefficient for bias dependence
      	of TF 				- 	0
      24 VTF 	voltage describing VBC
      	dependence of TF 		V 	infinite
      25 ITF 	high-current parameter for
      	effect on TF 			A	0			 *
      26 PTF 	excess phase at
      	freq=1.0/(TF*2PI) Hz 		deg 	0
      27 CJC 	B-C zero-bias depletion
      	capacitance 			F 	0 		2pF	 *
      28 VJC 	B-C built-in potential 		V 	0.75 		0.5
      29 MJC 	B-C junction exponential factor	- 	0.33 		0.5
      30 XCJC	fraction of B-C depletion
      	capacitance connected to
      	internal base node		-	1
      31 TR 	ideal reverse transit time 	sec 	0 		10ns
      32 CJS 	zero-bias collector-substrate
      	capacitance 			F 	0 		2pF	 *
      33 VJS 	substrate junction built-in
      	potential 			V 	0.75
      34 MJS 	substrate junction exponential
      	factor 				- 	0 		0.5
      35 XTB 	forward and reverse beta
      	temperature exponent 		- 	0
      36 EG 	energy gap for temperature
      	effect on IS 			eV 	1.11
      37 XTI 	temperature exponent for
      	effect on IS 			- 	3
      38 KF 	flicker-noise coefficient 	- 	0
      39 AF 	flicker-noise exponent 		- 	1
      40 FC 	coefficient for forward-bias
      	depletion capacitance formula 	- 	0.5
      41 TNOM	Parameter measurement temp	C 	27 		50
      
      
      
      3.4.5. Junction Field-Effect Transistors (JFETs)
      
      General form:
      
      	JXXXXXXX ND NG NS MNAME <AREA> <OFF> <IC=VDS, VGS> <TEMP=T>
      
      Examples:
      
      	J1 7 2 3 JM1 OFF
      
      ND, NG, and NS are the drain, gate, and source nodes, respectively. MNAME is
      the model name, AREA is the area factor, and OFF indicates an (optional)
      initial condition on the device for dc analysis. If the area factor is
      omitted, a value of 1.0 is assumed. The (optional) initial condition
      specification, using IC=VDS, VGS is intended for use with the UIC option on
      the .TRAN control line, when a transient analysis is desired starting from
      other than the quiescent operating point. See the .IC control line for a
      better way to set initial conditions. The (optional) TEMP value is the
      temperature at which this device is to operate, and overrides the temperature
      specification on the .OPTION control line.
      
      
      3.4.6. JFET Models (NJF/PJF)
      
      The JFET model is derived from the FET model of Shichman and Hodges. The dc
      characteristics are defined by the parameters VTO and BETA, which determine
      the variation of drain current with gate voltage, LAMBDA, which determines
      the output conductance, and IS, the saturation current of the two gate
      junctions. Two ohmic resistances, RD and RS, are included. Charge storage is
      modeled by nonlinear depletion layer capacitances for both gate junctions
      which vary as the -1/2 power of junction voltage and are defined by the
      parameters CGS, CGD, and PB.
      
      Note that in Spice3f and later, a fitting parameter B has been added. For
      details, see [9].
      
         name 	parameter 			units	default	example	area
      ------------------------------------------------------------------------------
      1  VTO 		threshold voltage (VTO 		V 	-2.0	-2.0
      2  BETA 	transconductance parameter () 	A/V 	1.0e-4 	1.0e-3	 *
      3  LAMBDA 	channel-length modulation
      		parameter (lambda) 		1/V 	0 	1.0e-4
      4  RD 		drain ohmic resistance 		Ohms  	0 	100	 *
      5  RS 		source ohmic resistance 	Ohms  	0	100	 *
      6  CGS 		zero-bias G-S junction
      		capacitance (Cgs) 		F 	0 	5pF	 *
      7  CGD 		zero-bias G-D junction
      		capacitance (Cgs) 		F 	0 	1pF	 *
      8  PB 		gate junction potential 	V 	1 	0.6
      9  IS 		gate junction saturation
      		current (Is) 			A 	1.0e-14	1.0e-14	 *
      10 B 		doping tail parameter 		- 	1 	1.1
      11 KF 		flicker noise coefficient 	- 	0
      12 AF 		flicker noise exponent 		- 	1
      13 FC 		coefficient for forward-bias
      		depletion capacitance formula  	- 	0.5
      14 TNOM 	parameter measurement temp	C	27	50
      
      
      
      3.4.7. MOSFETs
      
      General form:
      
      	MXXXXXXX ND NG NS NB MNAME <L=VAL> <W=VAL> <AD=VAL> <AS=VAL>
      	+ <PD=VAL> <PS=VAL> <NRD=VAL> <NRS=VAL> <OFF>
      	+ <IC=VDS, VGS, VBS> <TEMP=T>
      
      Examples:
      
      	M1 24 2 0 20 TYPE1
      	M31 2 17 6 10 MODM L=5U W=2U
      	M1 2 9 3 0 MOD1 L=10U W=5U AD=100P AS=100P PD=40U PS=40U
      
      ND, NG, NS, and NB are the drain, gate, source, and bulk (substrate) nodes,
      respectively. MNAME is the model name. L and W are the channel length and
      width, in meters. AD and AS are the areas of the drain and source diffusions,
      in meters2. Note that the suffix U specifies microns (1e-6 m) and P
      sq-microns (1e12 m2). If any of L, W, AD, or AS are not specified, default
      values are used. The use of defaults simplifies input file preparation, as
      well as the editing required if device geometries are to be changed. PD and
      PS are the perimeters of the drain and source junctions, in meters. NRD and
      NRS designate the equivalent number of squares of the drain and source
      diffusions; these values multiply the sheet resistance RSH specified on the
      .MODEL control line for an accurate representation of the parasitic series
      drain and source resistance of each transistor. PD and PS default to 0.0
      while NRD and NRS to 1.0. OFF indicates an (optional) initial condition on
      the device for dc analysis. The (optional) initial condition specification
      using IC=VDS, VGS, VBS is intended for use with the UIC option on the .TRAN
      control line, when a transient analysis is desired starting from other than
      the quiescent operating point. See the .IC control line for a better and more
      convenient way to specify transient initial conditions. The (optional) TEMP
      value is the temperature at which this device is to operate, and overrides
      the temperature specification on the .OPTION control line. The temperature
      specification is ONLY valid for level 1, 2, 3, and 6 MOSFETs, not for level 4
      or 5 (BSIM) devices.
      
      
      3.4.8. MOSFET Models (NMOS/PMOS)
      
      SPICE provides four MOSFET device models, which differ in the formulation of
      the I-V characteristic. The variable LEVEL specifies the model to be used:
      
      	LEVEL=1 -> Shichman-Hodges
      	LEVEL=2 -> MOS2 (as described in [1])
      	LEVEL=3 -> MOS3, a semi-empirical model(see [1])
      	LEVEL=4 -> BSIM (as described in [3])
      	LEVEL=5 -> new BSIM (BSIM2; as described in [5])
      	LEVEL=6 -> MOS6 (as described in [2])
      
      The dc characteristics of the level 1 through level 3 MOSFETs are defined by
      the device parameters VTO, KP, LAMBDA, PHI and GAMMA. These parameters are
      computed by SPICE if process parameters (NSUB, TOX, ...) are given, but
      user-specified values always override. VTO is positive (negative) for
      enhancement mode and negative (positive) for depletion mode N-channel
      (P-channel) devices. Charge storage is modeled by three constant capacitors,
      CGSO, CGDO, and CGBO which represent overlap capacitances, by the nonlinear
      thin-oxide capacitance which is distributed among the gate, source, drain,
      and bulk regions, and by the nonlinear depletion-layer capacitances for both
      substrate junctions divided into bottom and periphery, which vary as the MJ
      and MJSW power of junction voltage respectively, and are determined by the
      parameters CBD, CBS, CJ, CJSW, MJ, MJSW and PB. Charge storage effects are
      modeled by the piecewise linear voltages-dependent capacitance model proposed
      by Meyer. The thinoxide charge-storage effects are treated slightly different
      for the LEVEL=1 model. These voltagedependent capacitances are included only
      if TOX is specified in the input description and they are represented using
      Meyer's formulation.
      
      There is some overlap among the parameters describing the junctions, e.g. the
      reverse current can be input either as IS (in A) or as JS (in A/m2). Whereas
      the first is an absolute value the second is multiplied by AD and AS to give
      the reverse current of the drain and source junctions respectively. This
      methodology has been chosen since there is no sense in relating always
      junction characteristics with AD and AS entered on the device line; the areas
      can be defaulted. The same idea applies also to the zero-bias junction
      capacitances CBD and CBS (in F) on one hand, and CJ (in F/m2) on the other.
      The parasitic drain and source series resistance can be expressed as either
      RD and RS (in ohms) or RSH (in ohms/sq.), the latter being multiplied by the
      number of squares NRD and NRS input on the device line.
      
      A discontinuity in the MOS level 3 model with respect to the KAPPA parameter
      has been detected (see [10]). The supplied fix has been implemented in
      Spice3f2 and later. Since this fix may affect parameter fitting, the option
      "BADMOS3" may be set to use the old implementation (see the section on
      simulation variables and the ".OPTIONS" line).
      
      
      level 1, 2, 3 and 6 parameters:
      
         name		parameter				units	default	example
      --------------------------------------------------------------------------------
      1  LEVEL 	model index 				- 	1
      2  VTO 		zero-bias threshold voltage (VTO) 	V 	0.0 	1.0
      3  KP 		transconductance parameter 		A/V 	2.0e-5 	3.1e-5
      4  GAMMA 	bulk threshold parameter (g) 		V^0.5 	0.0 	0.37
      5  PHI 		surface potential (f) 			V 	0.6 	0.65
      6  LAMBDA 	channel-length modulation
      		(MOS1 and MOS2 only) (l) 		1/V 	0.0 	0.02
      7  RD 		drain ohmic resistance 			Ohms  	0.0 	1.0
      8  RS 		source ohmic resistance 		Ohms  	0.0 	1.0
      9  CBD 		zero-bias B-D junction capacitance 	F 	0.0 	20fF
      10 CBS 		zero-bias B-S junction capacitance 	F 	0.0 	20fF
      11 IS bulk 	junction saturation current (IS) 	A 	1.0e-14	1.0e-15
      12 PB bulk 	junction potential 			V 	0.8 	0.87
      13 CGSO 	gate-source overlap capacitance per
      		meter channel width 			F/m 	0.0	4.0e-11
      14 CGDO 	gate-drain overlap capacitance per
      		meter channel width 			F/m 	0.0 	4.0e-11
      15 CGBO 	gate-bulk overlap capacitance per
      		meter channel length 			F/m 	0.0 	2.0e-10
      16 RSH 		drain and source diffusion sheet
      		resistance 				Ohms/sqr 0.0 	10.0
      17 CJ 		zero-bias bulk junction bottom cap.
      		per sq-meter of junction area 		F/m 	0.0 	2.0e-4
      18 MJ 		bulk junction bottom grading coeff. 	- 	0.5 	0.5
      19 CJSW 	zero-bias bulk junction sidewall cap.
      		per meter of junction perimeter 	F/m 	0.0 	1.0e-9
      20 MJSW 	bulk junction sidewall grading coeff. 	- 	0.50(level1)
      								0.33(level2, 3)
      21 JS 		bulk junction saturation current per
      		sq-meter of junction area 		A/m 	1.0e-8
      22 TOX 		oxide thickness 			meter 	1.0e-7 	1.0e-7
      23 NSUB 	substrate doping 			1/cm 	0.0 	4.0e15
      24 NSS 		surface state density 			1/cm 	0.0 	1.0e10
      25 NFS 		fast surface state density 		1/cm 	0.0 	1.0e10
      26 TPG 		type of gate material:			- 	1.0
      			+1 opp. to substrate
      			-1 same as substrate
      			0 Al gate
      27 XJ 		metallurgical junction depth 		meter 	0.0 	1e-6
      28 LD 		lateral diffusion 			meter 	0.0 	0.8u
      29 UO 		surface mobility 			cm/Vs 	600 	700
      30 UCRIT 	critical field for mobility degradation
      		(MOS2 only) 				V/cm 	1.0e4 	1.0e4
      31 UEXP 	critical field exponent in mobility
      		degradation (MOS2 only) 		- 	0.0 	0.1
      32 UTRA 	transverse field coeff. (mobility)
      		(deleted for MOS2) 			- 	0.0 	0.3
      33 VMAX 	maximum drift velocity of carriers 	m/s 	0.0 	5.0e4
      34 NEFF 	total channel-charge (fixed and mobile)
      		coefficient (MOS2 only) 		- 	1.0 	5.0
      35 KF 		flicker noise coefficient 		- 	0.0 	1.0e-26
      36 AF 		flicker noise exponent 			- 	1.0 	1.2
      37 FC 		coefficient for forward-bias depletion
      		capacitance formula 			- 	0.5
      38 DELTA 	width effect on threshold voltage
      		(MOS2 and MOS3) 			- 	0.0 	1.0
      39 THETA 	mobility modulation (MOS3 only) 	1/V 	0.0 	0.1
      40 ETA 		static feedback (MOS3 only) 		- 	0.0 	1.0
      41 KAPPA 	saturation field factor (MOS3 only) 	- 	0.2 	0.5
      42 TNOM 	parameter measurement temperature 	C 	27 	50
      
      
      The level 4 and level 5 (BSIM1 and BSIM2) parameters are all values obtained
      from process characterization, and can be generated automatically. J. Pierret
      [4] describes a means of generating a 'process' file, and the program
      Proc2Mod provided with SPICE3 converts this file into a sequence of BSIM1
      ".MODEL" lines suitable for inclusion in a SPICE input file. Parameters
      marked below with an * in the l/w column also have corresponding parameters
      with a length and width dependency. For example, VFB is the basic parameter
      with units of Volts, and LVFB and WVFB also exist and have units of
      Volt-umeter The formula
      
      	           P         P
      	            L         W
      	P = P  + ------- + -------
      	     0    L         W
      	           eff.      eff.
      
      is used to evaluate the parameter for the actual device specified with
      
      	L          = L      - DL
               effective    input
      and
      
      	W          = W      - DW
               effective    input
      
      Note that unlike the other models in SPICE, the BSIM model is designed for
      use with a process characterization system that provides all the parameters,
      thus there are no defaults for the parameters, and leaving one out is
      considered an error. For an example set of parameters and the format of a
      process file, see the SPICE2 implementation notes[3].
      
      For more information on BSIM2, see reference [5].
      
      SPICE BSIM (level 4) parameters.
      
      name	parameter						units	l/w
      VFB 	flat-band voltage 					V	 *
      PHI 	surface inversion potential 				V	 *
      K1 	body effect coefficient 				V^0.5	 *
      K2 	drain/source depletion charge-sharing coefficient 	-	 *
      ETA 	zero-bias drain-induced barrier-lowering coefficient 	-	 *
      MUZ 	zero-bias mobility 					cm/V-s
      DL 	shortening of channel 					um
      DW 	narrowing of channel 					um
      U0 	zero-bias transverse-field mobility degradation coef	1/V	 *
      U1 	zero-bias velocity saturation coefficient 		um/V	 *
      X2MZ 	sens. of mobility to substrate bias at vds=0		cm/V-s *
      X2E 	sens. of drain-induced barrier lowering effect to
      	substrate bias 						1/V	 *
      X3E 	sens. of drain-induced barrier lowering effect to drain
      	bias at Vds=Vdd 					1/V	 *
      X2U0 	sens. of transverse field mobility degradation effect
      	to substrate bias 					V-	 *
      X2U1 	sens. of velocity saturation effect to substrate bias 	umV-	 *
      MUS 	mobility at zero substrate bias and at Vds=Vdd 		cm/V-s
      X2MS 	sens. of mobility to substrate bias at Vds=Vdd 		cm/V-s *
      X3MS 	sens. of mobility to drain bias at Vds=Vdd 		cm/V-s *
      X3U1 	sens. of velocity saturation effect on drain bias
      	at Vds=Vdd 						umV-	 *
      TOX 	gate oxide thickness 					um
      TEMP	temperature at which parameters were measured 		C
      VDD 	measurement bias range 					V
      CGDO 	gate-drain overlap capacitance per meter channel width 	F/m
      CGSO 	gate-source overlap capacitance per meter channel width	F/m
      CGBO 	gate-bulk overlap capacitance per meter channel length	F/m
      XPART 	gate-oxide capacitance-charge model flag		-
      N0 	zero-bias subthreshold slope coefficient 		-	 *
      NB 	sens. of subthreshold slope to substrate bias 		-	 *
      ND 	sens. of subthreshold slope to drain bias 		-	 *
      RSH 	drain and source diffusion sheet resistance 		Ohms/sqr
      JS 	source drain junction current density 			A/m
      PB 	built in potential of source drain junction 		V
      MJ 	Grading coefficient of source drain junction		-
      PBSW 	built in potential of source, drain junction sidewall 	V
      MJSW 	grading coefficient of source drain junction sidewall	-
      CJ 	Source drain junction capacitance per unit area 	F/m
      CJSW 	source drain junction sidewall capacitance per
      	unit length 						F/m
      WDF 	source drain junction default width 			m
      DELL 	Source drain junction length reduction 			m
      
      XPART = 0 selects a 40/60 drain/source charge partition in saturation, while
      XPART=1 selects a 0/100 drain/source charge partition.
      
      ND, NG, and NS are the drain, gate, and source nodes, respectively. MNAME is
      the model name, AREA is the area factor, and OFF indicates an (optional)
      initial condition on the device for dc analysis. If the area factor is
      omitted, a value of 1.0 is assumed. The (optional) initial condition
      specification, using IC=VDS, VGS is intended for use with the UIC option on
      the .TRAN control line, when a transient analysis is desired starting from
      other than the quiescent operating point. See the .IC control line for a
      better way to set initial conditions.
      
      
      
      3.4.9. MESFETs
      
      General form:
      
      	ZXXXXXXX ND NG NS MNAME <AREA> <OFF> <IC=VDS, VGS>
      
      Examples:
      
      	Z1 7 2 3 ZM1 OFF
      
      
      
      3.4.10. MESFET Models (NMF/PMF)
      
      The MESFET model is derived from the GaAs FET model of Statz et al. as
      described in [11]. The dc characteristics are defined by the parameters VTO,
      B, and BETA, which determine the variation of drain current with gate
      voltage, ALPHA, which determines saturation voltage, and LAMBDA, which
      determines the output conductance. The formula are given by:
      
              B (V   - V )    |     |       V   |3 |
                  gs    T      |     |        ds |  |
       I  = -----------------  | 1 - | 1 - A --- |  | (1 + L V  )
        d    1 + b(V   - V )   |     |        3  |  |         ds
                    gs    T    |     |           |  |
      
                      3
      for  0 < V   < ---
                ds    A
      
      and
      
            B (V   - V )
                gs    T                               3
      I  = ---------------- (1 + L V  )    for V   > ---
       d    1 + b(V   - V )         ds          ds    A
                   gs    T
      
      Two ohmic resistances, RD and RS, are included. Charge storage is modeled by
      total gate charge as a function of gate-drain and gate-source voltages and is
      defined by the parameters CGS, CGD, and PB.
      
         name	   parameter				units	default	example	area
      ------------------------------------------------------------------------------
      1  VTO 	   pinch-off voltage 			V 	-2.0 	-2.0
      2  BETA    transconductance parameter 		A/V2 	1.0e-4 	1.0e-3	 *
      3  B 	   doping tail extending parameter 	1/V 	0.3 	0.3	 *
      4  ALPHA   saturation voltage parameter		1/V 	2 	2	 *
      5  LAMBDA  channel-length modulationparameter 	1/V 	0 	1.0e-4
      6  RD 	   drain ohmic resistance 		Ohms  	0 	100	 *
      7  RS 	   source ohmic resistance 		Ohms  	0 	100	 *
      8  CGS 	   zero-bias G-S junction capacitance 	F 	0 	5pF	 *
      9  CGD 	   zero-bias G-D junction capacitance 	F 	0 	1pF	 *
      10 PB 	   gate junction potential 		V 	1 	0.6
      11 KF 	   flicker noise coefficient 		- 	0
      12 AF 	   flicker noise exponent 		- 	1
      13 FC 	   coefficient for forward-bias
      	   depletion capacitance formula	- 	0.5
      
      
      
      
      4. ANALYSES AND OUTPUT CONTROL
      
      The following command lines are for specifying analyses or plots within the
      circuit description file. Parallel commands exist in the interactive command
      interpreter (detailed in the following section). Specifying analyses and
      plots (or tables) in the input file is useful for batch runs. Batch mode is
      entered when either the -b option is given or when the default input source
      is redirected from a file. In batch mode, the analyses specified by the
      control lines in the input file (e.g. ".ac", ".tran", etc.) are immediately
      executed (unless ".control" lines exists; see the section on the interactive
      command interpretor). If the -r rawfile option is given then all data
      generated is written to a Spice3 rawfile. The rawfile may be read by either
      the interactive mode of Spice3 or by nutmeg; see the previous section for
      details. In this case, the .SAVE line (see below) may be used to record the
      value of internal device variables (see Appendix B).
      
      If a rawfile is not specified, then output plots (in "line-printer" form) and
      tables can be printed according to the .PRINT, .PLOT, and .FOUR control
      lines, described next. .PLOT, .PRINT, and .FOUR lines are meant for
      compatibility with Spice2.
      
      
      4.1. SIMULATOR VARIABLES (.OPTIONS)
      
      Various parameters of the simulations available in Spice3 can be altered to
      control the accuracy, speed, or default values for some devices. These
      parameters may be changed via the "set" command (described later in the
      section on the interactive front-end) or via the ".OPTIONS" line:
      
      General form:
      
      	.OPTIONS OPT1 OPT2 ... (or OPT=OPTVAL ...)
      
      Examples:
      
      	.OPTIONS RELTOL=.005 TRTOL=8
      
      The options line allows the user to reset program control and user options
      for specific simulation purposes. Additional options for Nutmeg may be
      specified as well and take effect when Nutmeg reads the input file. Options
      specified to Nutmeg via the 'set' command are also passed on to SPICE3 as if
      specified on a .OPTIONS line. See the following section on the interactive
      command interpreter for the parameters which may be set with a .OPTIONS line
      and the format of the 'set' command. Any combination of the following options
      may be included, in any order. 'x' (below) represents some positive number.
      
      option		effect
      ---------------------------------------------------------------------------
      ABSTOL=x	resets the absolute current error tolerance of the program.
      		The default value is 1 picoamp.
      BADMOS3 	Use the older version of the MOS3 model with the "kappa"
      		discontinuity.
      CHGTOL=x 	resets the charge tolerance of the program. The default
      		value is 1.0e-14.
      DEFAD=x 	resets the value for MOS drain diffusion area; the
      		default is 0.0.
      DEFAS=x 	resets the value for MOS source diffusion area; the
      		default is 0.0.
      DEFL=x		resets the value for MOS channel length; the default is
      		100.0 micrometer.
      DEFW=x		resets the value for MOS channel width; the default is
      		100.0 micrometer.
      GMIN=x		resets the value of GMIN, the minimum conductance allowed
      		by the program. The default value is 1.0e-12.
      ITL1=x		resets the dc iteration limit. The default is 100.
      ITL2=x		resets the dc transfer curve iteration limit. The default is 50.
      ITL3=x		resets the lower transient analysis iteration limit. the
      		default value is 4. (Note: not implemented in Spice3).
      ITL4=x		resets the transient analysis timepoint iteration limit.
      		the default is 10.
      ITL5=x		resets the transient analysis total iteration limit.
      		the default is 5000. Set
      ITL5=0		to omit this test. (Note: not implemented in Spice3).
      KEEPOPINFO	Retain the operating point information when either an AC,
      		Distortion, or Pole-Zero analysis is run. This is
      		particularly useful if thecircuit is large and you do not
      		want to run a (redundant) ".OP" analysis.
      METHOD=name 	sets the numerical integration method used by SPICE. Possible
      		names are "Gear" or "trapezoidal" (or just "trap"). The
      		default is trapezoidal.
      PIVREL=x 	resets the relative ratio between the largest column entry
      		and an acceptable pivot value. The default value is 1.0e-3.
      		In the numerical pivoting algorithm the allowed minimum pivot
      		value is determined by EPSREL=AMAX1(PIVREL*MAXVAL, PIVTOL)
      		where MAXVAL is the maximum element in the column where a
      		pivot is sought (partial pivoting).
      PIVTOL=x 	resets the absolute minimum value for a matrix entry to be
      		accepted as a pivot. The default value is 1.0e-13.
      RELTOL=x	resets the relative error tolerance of the program. The
      		default value is 0.001 (0.1%).
      TEMP=x		Resets the operating temperature of the circuit. The default
      		value is 27 deg C (300deg K). TEMP can be overridden by a
      		temperature specification on any temperature dependent instance.
      TNOM=x		resets the nominal temperature at which device parameters are
      		measured. The default value is 27 deg C (300 degK). TNOM can
      		be overridden by a specification on any temperature dependent
      		device model.
      TRTOL=x		resets the transient error tolerance. The default value is
      		7.0. This parameter is an estimate of the factor by which
      		SPICE overestimates the actual truncation error.
      
      TRYTOCOMPACT	Applicable only to the LTRA model. When specified, the
      		simulator tries to condense LTRA transmission lines' past
      		history of input voltages and currents.
      
      VNTOL=x		resets the absolute voltage error tolerance of the program.
      		The default value is 1 microvolt.
      
      
      In addition, the following options have the listed effect when operating in
      spice2 emulation mode:
      
      option	effect
      ---------------------------------------------------------------------------
      ACCT 	causes accounting and run time statistics to be printed
      LIST 	causes the summary listing of the input data to be printed
      NOMOD 	suppresses the printout of the model parameters
      NOPAGE 	suppresses page ejects NODE causes the printing of the node table.
      OPTS 	causes the option values to be printed.
      
      
      
      4.2. INITIAL CONDITIONS
      
      
      4.2.1. .NODESET: Specify Initial Node Voltage Guesses
      
      General form:
      
      	.NODESET V(NODNUM)=VAL V(NODNUM)=VAL ...
      
      Examples:
      
      	.NODESET V(12)=4.5 V(4)=2.23
      
      The Nodeset line helps the program find the dc or initial transient solution
      by making a preliminary pass with the specified nodes held to the given
      voltages. The restriction is then released and the iteration continues to the
      true solution. The .NODESET line may be necessary for convergence on bistable
      or astable circuits. In general, this line should not be necessary.
      
      
      4.2.2. .IC: Set Initial Conditions
      
      General form:
      
      	.IC V(NODNUM)=VAL V(NODNUM)=VAL ...
      
      Examples:
      
      	.IC V(11)=5 V(4)=-5 V(2)=2.2
      
      The IC line is for setting transient initial conditions. It has two different
      interpretations, depending on whether the UIC parameter is specified on the
      .TRAN control line. Also, one should not confuse this line with the .NODESET
      line. The .NODESET line is only to help dc convergence, and does not affect
      final bias solution (except for multi-stable circuits). The two
      interpretations of this line are as follows:
      
      1. When the UIC parameter is specified on the .TRAN line, then the node
      voltages specified on the .IC control line are used to compute the capacitor,
      diode, BJT, JFET, and MOSFET initial conditions. This is equivalent to
      specifying the IC=... parameter on each device line, but is much more
      convenient. The IC=... parameter can still be specified and takes precedence
      over the .IC values. Since no dc bias (initial transient) solution is
      computed before the transient analysis, one should take care to specify all
      dc source voltages on the .IC control line if they are to be used to compute
      device initial conditions.
      
      2. When the UIC parameter is not specified on the .TRAN control line, the dc
      bias (initial transient) solution is computed before the transient analysis.
      In this case, the node voltages specified on the .IC control line is forced
      to the desired initial values during the bias solution. During transient
      analysis, the constraint on these node voltages is removed. This is the
      preferred method since it allows SPICE to compute a consistent dc solution.
      
      
      
      4.3. ANALYSES
      
      
      4.3.1. .AC: Small-Signal AC Analysis
      
      General form:
      
      	.AC DEC ND FSTART FSTOP
      	.AC OCT NO FSTART FSTOP
      	.AC LIN NP FSTART FSTOP
      
      Examples:
      
      	.AC DEC 10 1 10K
      	.AC DEC 10 1K 100MEG
      	.AC LIN 100 1 100HZ
      
      DEC stands for decade variation, and ND is the number of points per decade.
      OCT stands for octave variation, and NO is the number of points per octave.
      LIN stands for linear variation, and NP is the number of points. FSTART is
      the starting frequency, and FSTOP is the final frequency. If this line is
      included in the input file, SPICE performs an AC analysis of the circuit over
      the specified frequency range. Note that in order for this analysis to be
      meaningful, at least one independent source must have been specified with an
      ac value.
      
      
      4.3.2. .DC: DC Transfer Function
      
      General form:
      
      	.DC SRCNAM VSTART VSTOP VINCR [SRC2 START2 STOP2 INCR2]
      
      Examples:
      
      	.DC VIN 0.25 5.0 0.25
      	.DC VDS 0 10 .5 VGS 0 5 1
      	.DC VCE 0 10 .25 IB 0 10U 1U
      
      The DC line defines the dc transfer curve source and sweep limits (again with
      capacitors open and inductors shorted). SRCNAM is the name of an independent
      voltage or current source. VSTART, VSTOP, and VINCR are the starting, final,
      and incrementing values respectively. The first example causes the value of
      the voltage source VIN to be swept from 0.25 Volts to 5.0 Volts in increments
      of 0.25 Volts. A second source (SRC2) may optionally be specified with
      associated sweep parameters. In this case, the first source is swept over its
      range for each value of the second source. This option can be useful for
      obtaining semiconductor device output characteristics. See the second example
      circuit description in Appendix A.
      
      
      4.3.3. .DISTO: Distortion Analysis
      
      General form:
      
      	.DISTO DEC ND FSTART FSTOP <F2OVERF1>
      	.DISTO OCT NO FSTART FSTOP <F2OVERF1>
      	.DISTO LIN NP FSTART FSTOP <F2OVERF1>
      
      Examples:
      
      	.DISTO DEC 10 1kHz 100Mhz
      	.DISTO DEC 10 1kHz 100Mhz 0.9
      
      The Disto line does a small-signal distortion analysis of the circuit. A
      multi-dimensional Volterra series analysis is done using multi-dimensional
      Taylor series to represent the nonlinearities at the operating point. Terms
      of up to third order are used in the series expansions.
      
      If the optional parameter F2OVERF1 is not specified, .DISTO does a harmonic
      analysis - i.e., it analyses distortion in the circuit using only a single
      input frequency F1, which is swept as specified by arguments of the .DISTO
      command exactly as in the .AC command. Inputs at this frequency may be
      present at more than one input source, and their magnitudes and phases are
      specified by the arguments of the DISTOF1 keyword in the input file lines for
      the input sources (see the description for independent sources). (The
      arguments of the DISTOF2 keyword are not relevant in this case). The analysis
      produces information about the A.C. values of all node voltages and branch
      currents at the harmonic frequencies 2F1 and 3F1, vs. the input frequency F1
      as it is swept. (A value of 1 (as a complex distortion output) signifies
      cos(2p(2F1)t) at 2F1 and cos(2p(3F1)t) at 3F1, using the convention that 1 at
      the input fundamental frequency is equivalent to cos(2pF1t).) The distortion
      component desired (2F1 or 3F1) can be selected using commands in nutmeg, and
      then printed or plotted. (Normally, one is interested primarily in the
      magnitude of the harmonic components, so the magnitude of the AC distortion
      value is looked at). It should be noted that these are the A.C. values of the
      actual harmonic components, and are not equal to HD2 and HD3. To obtain HD2
      and HD3, one must divide by the corresponding A.C. values at F1, obtained
      from an .AC line. This division can be done using nutmeg commands.
      
      If the optional F2OVERF1 parameter is specified, it should be a real number
      between (and not equal to) 0.0 and 1.0; in this case, .DISTO does a spectral
      analysis. It considers the circuit with sinusoidal inputs at two different
      frequencies F1 and F2. F1 is swept according to the .DISTO control line
      options exactly as in the .AC control line. F2 is kept fixed at a single
      frequency as F1 sweeps - the value at which it is kept fixed is equal to
      F2OVERF1 times FSTART. Each independent source in the circuit may potentially
      have two (superimposed) sinusoidal inputs for distortion, at the frequencies
      F1 and F2. The magnitude and phase of the F1 component are specified by the
      arguments of the DISTOF1 keyword in the source's input line (see the
      description of independent sources); the magnitude and phase of the F2
      component are specified by the arguments of the DISTOF2 keyword. The analysis
      produces plots of all node voltages/branch currents at the intermodulation
      product frequencies F1 + F2, F1 - F2, and (2 F1) - F2, vs the swept frequency
      F1. The IM product of interest may be selected using the setplot command, and
      displayed with the print and plot commands. It is to be noted as in the
      harmonic analysis case, the results are the actual AC voltages and currents
      at the intermodulation frequencies, and need to be normalized with respect to
      .AC values to obtain the IM parameters.
      
      If the DISTOF1 or DISTOF2 keywords are missing from the description of an
      independent source, then that source is assumed to have no input at the
      corresponding frequency. The default values of the magnitude and phase are
      1.0 and 0.0 respectively. The phase should be specified in degrees.
      
      It should be carefully noted that the number F2OVERF1 should ideally be an
      irrational number, and that since this is not possible in practice, efforts
      should be made to keep the denominator in its fractional representation as
      large as possible, certainly above 3, for accurate results (i.e., if F2OVERF1
      is represented as a fraction A/B, where A and B are integers with no common
      factors, B should be as large as possible; note that A < B because F2OVERF1
      is constrained to be < 1). To illustrate why, consider the cases where
      F2OVERF1 is 49/100 and 1/2. In a spectral analysis, the outputs produced are
      at F1 + F2, F1 - F2 and 2 F1 - F2. In the latter case, F1 - F2 = F2, so the
      result at the F1-F2 component is erroneous because there is the strong
      fundamental F2 component at the same frequency. Also, F1 + F2 = 2 F1 - F2 in
      the latter case, and each result is erroneous individually. This problem is
      not there in the case where F2OVERF1 = 49/100, because F1-F2 = 51/100 F1 < >
      49/100 F1 = F2. In this case, there are two very closely spaced frequency
      components at F2 and F1 - F2. One of the advantages of the Volterra series
      technique is that it computes distortions at mix frequencies expressed
      symbolically (i.e. n F1 +- m F2), therefore one is able to obtain the
      strengths of distortion components accurately even if the separation between
      them is very small, as opposed to transient analysis for example. The
      disadvantage is of course that if two of the mix frequencies coincide, the
      results are not merged together and presented (though this could presumably
      be done as a postprocessing step). Currently, the interested user should keep
      track of the mix frequencies himself or herself and add the distortions at
      coinciding mix frequencies together should it be necessary.
      
      
      4.3.4. .NOISE: Noise Analysis
      
      General form:
      
      	.NOISE V(OUTPUT <,REF>) SRC ( DEC | LIN | OCT ) PTS FSTART FSTOP
      	+ <PTS_PER_SUMMARY>
      
      Examples:
      
      	.NOISE V(5) VIN DEC 10 1kHZ 100Mhz
      	.NOISE V(5,3) V1 OCT 8 1.0 1.0e6 1
      
      The Noise line does a noise analysis of the circuit. OUTPUT is the node at
      which the total output noise is desired; if REF is specified, then the noise
      voltage V(OUTPUT) - V(REF) is calculated. By default, REF is assumed to be
      ground. SRC is the name of an independent source to which input noise is
      referred. PTS, FSTART and FSTOP are .AC type parameters that specify the
      frequency range over which plots are desired. PTS_PER_SUMMARY is an optional
      integer; if specified, the noise contributions of each noise generator is
      produced every PTS_PER_SUMMARY frequency points.
      
      
      The .NOISE control line produces two plots - one for the Noise Spectral
      Density curves and one for the total Integrated Noise over the specified
      frequency range. All noise voltages/currents are in squared units (V2/Hz and
      A2/Hz for spectral density, V2 and A2 for integrated noise).
      
      
      4.3.5. .OP: Operating Point Analysis
      
      General form:
      
      	.OP
      
      The inclusion of this line in an input file directs SPICE to determine the dc
      operating point of the circuit with inductors shorted and capacitors opened.
      Note: a DC analysis is automatically performed prior to a transient analysis
      to determine the transient initial conditions, and prior to an AC
      small-signal, Noise, and Pole-Zero analysis to determine the linearized,
      small-signal models for nonlinear devices (see the KEEPOPINFO variable
      above).
      
      
      4.3.6. .PZ: Pole-Zero Analysis
      
      General form:
      
      	.PZ NODE1 NODE2 NODE3 NODE4 CUR POL
      	.PZ NODE1 NODE2 NODE3 NODE4 CUR ZER
      	.PZ NODE1 NODE2 NODE3 NODE4 CUR PZ
      	.PZ NODE1 NODE2 NODE3 NODE4 VOL POL
      	.PZ NODE1 NODE2 NODE3 NODE4 VOL ZER
      	.PZ NODE1 NODE2 NODE3 NODE4 VOL PZ
      
      Examples:
      
      	.PZ 1 0 3 0 CUR POL
      	.PZ 2 3 5 0 VOL ZER
      	.PZ 4 1 4 1 CUR PZ
      
      CUR stands for a transfer function of the type (output voltage)/(input
      current) while VOL stands for a transfer function of the type (output
      voltage)/(input voltage). POL stands for pole analysis only, ZER for zero
      analysis only and PZ for both. This feature is provided mainly because if
      there is a nonconvergence in finding poles or zeros, then, at least the other
      can be found. Finally, NODE1 and NODE2 are the two input nodes and NODE3 and
      NODE4 are the two output nodes. Thus, there is complete freedom regarding the
      output and input ports and the type of transfer function.
      
      In interactive mode, the command syntax is the same except that the first
      field is PZ instead of .PZ. To print the results, one should use the command
      'print all'.
      
      
      4.3.7. .SENS: DC or Small-Signal AC Sensitivity Analysis
      
      General form:
      
      	.SENS OUTVAR
      	.SENS OUTVAR AC DEC ND FSTART FSTOP
      	.SENS OUTVAR AC OCT NO FSTART FSTOP
      	.SENS OUTVAR AC LIN NP FSTART FSTOP
      
      Examples:
      
      	.SENS V(1,OUT)
      	.SENS V(OUT) AC DEC 10 100 100k
      	.SENS I(VTEST)
      
      The sensitivity of OUTVAR to all non-zero device parameters is calculated
      when the SENS analysis is specified. OUTVAR is a circuit variable (node
      voltage or voltage-source branch current). The first form calculates
      sensitivity of the DC operating-point value of OUTVAR. The second form
      calculates sensitivity of the AC values of OUTVAR. The parameters listed for
      AC sensitivity are the same as in an AC analysis (see ".AC" above). The
      output values are in dimensions of change in output per unit change of input
      (as opposed to percent change in output or per percent change of input).
      
      
      4.3.8. .TF: Transfer Function Analysis
      
      General form:
      
      	.TF OUTVAR INSRC
      
      Examples:
      
      	.TF V(5, 3) VIN
      	.TF I(VLOAD) VIN
      
      The TF line defines the small-signal output and input for the dc small-signal
      analysis. OUTVAR is the small-signal output variable and INSRC is the
      small-signal input source. If this line is included, SPICE computes the dc
      small-signal value of the transfer function (output/input), input resistance,
      and output resistance. For the first example, SPICE would compute the ratio
      of V(5, 3) to VIN, the small-signal input resistance at VIN, and the
      small-signal output resistance measured across nodes 5 and 3.
      
      
      4.3.9. .TRAN: Transient Analysis
      
      General form:
      
      	.TRAN TSTEP TSTOP <TSTART <TMAX>>
      
      Examples:
      
      	.TRAN 1NS 100NS
      	.TRAN 1NS 1000NS 500NS
      	.TRAN 10NS 1US
      
      TSTEP is the printing or plotting increment for line-printer output. For use
      with the post-processor, TSTEP is the suggested computing increment. TSTOP is
      the final time, and TSTART is the initial time. If TSTART is omitted, it is
      assumed to be zero. The transient analysis always begins at time zero. In the
      interval <zero, TSTART>, the circuit is analyzed (to reach a steady state),
      but no outputs are stored. In the interval <TSTART, TSTOP>, the circuit is
      analyzed and outputs are stored. TMAX is the maximum stepsize that SPICE
      uses; for default, the program chooses either TSTEP or (TSTOP-TSTART)/50.0,
      whichever is smaller. TMAX is useful when one wishes to guarantee a computing
      interval which is smaller than the printer increment, TSTEP.
      
      UIC (use initial conditions) is an optional keyword which indicates that the
      user does not want SPICE to solve for the quiescent operating point before
      beginning the transient analysis. If this keyword is specified, SPICE uses
      the values specified using IC=... on the various elements as the initial
      transient condition and proceeds with the analysis. If the .IC control line
      has been specified, then the node voltages on the .IC line are used to
      compute the initial conditions for the devices. Look at the description on
      the .IC control line for its interpretation when UIC is not specified.
      
      
      4.4. BATCH OUTPUT
      
      
      4.4.1. .SAVE Lines
      
      General form:
      
      	.SAVE vector vector vector ...
      
      Examples:
      
      	.SAVE i(vin) input output
      	.SAVE @m1[id]
      
      The vectors listed on the .SAVE line are recorded in the rawfile for use
      later with spice3 or nutmeg (nutmeg is just the data-analysis half of spice3,
      without the ability to simulate). The standard vector names are accepted. If
      no .SAVE line is given, then the default set of vectors are saved (node
      voltages and voltage source branch currents). If .SAVE lines are given, only
      those vectors specified are saved. For more discussion on internal device
      data, see Appendix B. See also the section on the interactive command
      interpretor for information on how to use the rawfile.
      
      
      4.4.2. .PRINT Lines General form:
      
      	.PRINT PRTYPE OV1 <OV2 ... OV8>
      
      Examples:
      
      	.PRINT TRAN V(4) I(VIN)
      	.PRINT DC V(2) I(VSRC) V(23, 17)
      	.PRINT AC VM(4, 2) VR(7) VP(8, 3)
      
      The Print line defines the contents of a tabular listing of one to eight
      output variables. PRTYPE is the type of the analysis (DC, AC, TRAN, NOISE, or
      DISTO) for which the specified outputs are desired. The form for voltage or
      current output variables is the same as given in the previous section for the
      print command; Spice2 restricts the output variable to the following forms
      (though this restriction is not enforced by Spice3):
      
      V(N1<,N2>)
      
      specifies the voltage difference between nodes N1 and N2. If N2 (and the
      preceding comma) is omitted, ground (0) is assumed. See the print command in
      the previous section for more details. For compatibility with spice2, the
      following five additional values can be accessed for the ac analysis by
      replacing the "V" in V(N1,N2) with:
      
      	VR - real part
      	VI - imaginary part
      	VM - magnitude
      	VP - phase
      	VDB - 20 log10(magnitude)
      
      I(VXXXXXXX) specifies the current flowing in the independent voltage source
      named VXXXXXXX. Positive current flows from the positive node, through the
      source, to the negative node. For the ac analysis, the corresponding
      replacements for the letter I may be made in the same way as described for
      voltage outputs.
      
      Output variables for the noise and distortion analyses have a different
      general form from that of the other analyses.
      
      There is no limit on the number of .PRINT lines for each type of analysis.
      
      
      4.4.3. .PLOT Lines
      
      General form:
      
      	.PLOT PLTYPE OV1 <(PLO1, PHI1)> <OV2 <(PLO2, PHI2)> ... OV8>
      
      Examples:
      
      	.PLOT DC V(4) V(5) V(1)
      	.PLOT TRAN V(17, 5) (2, 5) I(VIN) V(17) (1, 9)
      	.PLOT AC VM(5) VM(31, 24) VDB(5) VP(5)
      	.PLOT DISTO HD2 HD3(R) SIM2
      	.PLOT TRAN V(5, 3) V(4) (0, 5) V(7) (0, 10)
      
      The Plot line defines the contents of one plot of from one to eight output
      variables. PLTYPE is the type of analysis (DC, AC, TRAN, NOISE, or DISTO) for
      which the specified outputs are desired. The syntax for the OVI is identical
      to that for the .PRINT line and for the plot command in the interactive mode.
      
      The overlap of two or more traces on any plot is indicated by the letter X.
      When more than one output variable appears on the same plot, the first
      variable specified is printed as well as plotted. If a printout of all
      variables is desired, then a companion .PRINT line should be included.
      
      There is no limit on the number of .PLOT lines specified for each type of
      analysis.
      
      
      4.4.4. .FOUR: Fourier Analysis of Transient Analysis Output
      
      General form:
      
      	.FOUR FREQ OV1 <OV2 OV3 ...>
      
      Examples:
      
      	.FOUR 100K V(5)
      
      The Four (or Fourier) line controls whether SPICE performs a Fourier analysis
      as a part of the transient analysis. FREQ is the fundamental frequency, and
      OV1, ..., are the output variables for which the analysis is desired. The
      Fourier analysis is performed over the interval <TSTOP-period, TSTOP>, where
      TSTOP is the final time specified for the transient analysis, and period is
      one period of the fundamental frequency. The dc component and the first nine
      harmonics are determined. For maximum accuracy, TMAX (see the .TRAN line)
      should be set to period/100.0 (or less for very highQ circuits).
      
      
      
      
      5. INTERACTIVE INTERPRETER
      
      Spice3 consists of a simulator and a front-end for data analysis and
      plotting. The front-end may be run as a separate "stand-alone" program under
      the name Nutmeg.
      
      Command Synopsis
      
      bspice [-q] [-r rawfile] [input file ... ]
      
      Options are:
       
      -r rawfile [this is the only one that applies to bspice]
      Use rawfile as the default file into which the results of the simulation are
      saved. This option is valid for Spice3 only.
      
      -q quiet
      Don't print out the input card (with included files) when finished
      processing. Note this only a valid switch for Guy Griffin's and Frank/Eric
      vsn de Pol's bspice ports. Quiet is off by default.
      
      
      
      5.6. MISCELLANEOUS
      
      There are a number of pre-defined constants in nutmeg and bspice. They are:
      
      	pi	p (3.14159...)
      	e	The base of natural logarithms (2.71828...)
      	c	The speed of light (299,792,500 m/sec)
      	i	The square root of -1
      	kelvin	Absolute 0 in Centigrade (-273.15 oC)
      	echarge	The charge on an electron (1.6021918e-19 C)
      	boltz	Boltzman's constant (1.3806226e-23)
      	planck	Planck's constant (h = 6.626200e-34)
      
      These are all in MKS units. If you have another variable with a name that
      conflicts with one of these then it takes precedence.
      
      
      6. BIBLIOGRAPHY
      
      [1] A. Vladimirescu and S. Liu, The Simulation of MOS Integrated Circuits
      Using SPICE2 ERL Memo No. ERL M80/7, Electronics Research Laboratory
      University of California, Berkeley, October 1980
      
      [2] T. Sakurai and A. R. Newton, A Simple MOSFET Model for Circuit Analysis
      and its application to CMOS gate delay analysis and series-connected MOSFET
      Structure ERL Memo No. ERL M90/19, Electronics Research Laboratory,
      University of California, Berkeley, March 1990
      
      [3] B. J. Sheu, D. L. Scharfetter, and P. K. Ko, SPICE2 Implementation of
      BSIM ERL Memo No. ERL M85/42, Electronics Research Laboratory University of
      California, Berkeley, May 1985
      
      [4] J. R. Pierret, A MOS Parameter Extraction Program for the BSIM Model ERL
      Memo Nos. ERL M84/99 and M84/100, Electronics Research Laboratory University
      of California, Berkeley, November 1984
      
      [5] Min-Chie Jeng, Design and Modeling of Deep-Submicrometer MOSFETSs ERL
      Memo Nos. ERL M90/90, Electronics Research Laboratory University of
      California, Berkeley, October 1990
      
      [6] Soyeon Park, Analysis and SPICE implementation of High Temperature
      Effects on MOSFET, Master's thesis, University of California, Berkeley,
      December 1986.
      
      [7] Clement Szeto, Simulator of Temperature Effects in MOSFETs (STEIM),
      Master's thesis, University of California, Berkeley, May 1988.
      
      [8] J.S. Roychowdhury and D.O. Pederson, Efficient Transient Simulation of
      Lossy Interconnect, Proc. of the 28th ACM/IEEE Design Automation Conference,
      June 17-21 1991, San Francisco
      
      [9] A. E. Parker and D. J. Skellern, An Improved FET Model for Computer
      Simulators, IEEE Trans CAD, vol. 9, no. 5, pp. 551-553, May 1990.
      
      [10] R. Saleh and A. Yang, Editors, Simulation and Modeling, IEEE Circuits
      and Devices, vol. 8, no. 3, pp. 7-8 and 49, May 1992
      
      [11] H.Statz et al., GaAs FET Device and Circuit Simulation in SPICE, IEEE
      Transactions on Electron Devices, V34, Number 2, February, 1987 pp160-169.
