; > <StrongED$Dir>.h.RegNames
; StrongED$Mode = ObjAsm
; StrongED$WrapWidth = 96

; ARM register names

R0      RN     0
R1      RN     1
R2      RN     2
R3      RN     3
R4      RN     4
R5      RN     5
R6      RN     6
R7      RN     7
R8      RN     8
R9      RN     9
R10     RN     10
R11     RN     11
R12     RN     12
R13     RN     13
R14     RN     14
R15     RN     15

SP      RN     13
LR      RN     14
PC      RN     15

; ARM register names again

r0      RN     0
r1      RN     1
r2      RN     2
r3      RN     3
r4      RN     4
r5      RN     5
r6      RN     6
r7      RN     7
r8      RN     8
r9      RN     9
r10     RN     10
r11     RN     11
r12     RN     12
r13     RN     13
r14     RN     14
r15     RN     15

sp      RN     13
lr      RN     14
pc      RN     15

; Floating point registers

F0      FN     0
F1      FN     1
F2      FN     2
F3      FN     3
F4      FN     4
F5      FN     5
F6      FN     6
F7      FN     7

f0      FN     0
f1      FN     1
f2      FN     2
f3      FN     3
f4      FN     4
f5      FN     5
f6      FN     6
f7      FN     7

;  Define APCS standard register names. Note: This is APCS_R

a1      RN      r0
a2      RN      r1
a3      RN      r2
a4      RN      r3
v1      RN      r4
v2      RN      r5
v3      RN      r6
v4      RN      r7
v5      RN      r8
v6      RN      r9
sl      RN      r10
fp      RN      r11
ip      RN      r12
;sp      RN      r13  ;we can not redefine these as AS doesn't like that
;lr      RN      r14
;pc      RN      r15

;  Use the CN directive to define co-processor register names

c0      CN      0
c1      CN      1
c2      CN      2
c3      CN      3
c4      CN      4
c5      CN      5
c6      CN      6
c7      CN      7
c8      CN      8
c9      CN      9
c10     CN      10
c11     CN      11
c12     CN      12
c13     CN      13
c14     CN      14
c15     CN      15

;  Use the CP directive to define co-processor names

cp0     CP      0
cp1     CP      1
cp2     CP      2
cp3     CP      3
cp4     CP      4
cp5     CP      5
cp6     CP      6
cp7     CP      7
cp8     CP      8
cp9     CP      9
cp10    CP      10
cp11    CP      11
cp12    CP      12
cp13    CP      13
cp14    CP      14
cp15    CP      15

;  Status register masks

Fflag   EQU     1:SHL:26
Iflag   EQU     1:SHL:27
Vflag   EQU     1:SHL:28
Cflag   EQU     1:SHL:29
Zflag   EQU     1:SHL:30
Nflag   EQU     1:SHL:31

        END
