/*
 * Some handy 16F627x things
 *
 */

#include_only_once

#include <stdmac>
#include <tmr0ps>
#include <vref>
#include <serial>

// with FOSC2 low
enum	FOSC0_LP, FOSC0_XT, FOSC0_HS, FOSC0_EC;

// with FOSC2 high
enum	FOSC1_INT, FOSC1_INT_RA6, FOSC1_ER, FOSC1_ER_RA6;

// Prescaler on timer 0 (PS with PSA=0)
enum	PST0_2, PST0_4, PST0_8, PST0_16,
	PST0_32, PST0_64, PST0_128, PST0_256;

// Prescaler on WDT (PS with PSA=1)
enum	PSWDT_1, PSWDT_2, PSWDT_4, PSWDT_8,
	PSWDT_16, PSWDT_32, PSWDT_64, PSWDT_128;

// Prescaler on timer 1 (T1CKPS)
enum	PST1_1, PST1_2, PST1_4, PST1_8;

// Prescaler on timer 2 (T2CKPS)
enum	PST2_1, PST2_4, PST2_16;

// Postscaler on timer 2  (TOUTPS)
enum	OPS_1, OPS_2, OPS_3, OPS_4, OPS_5, OPS_6, OPS_7, OPS_8,
	OPS_9, OPS_10, OPS_11, OPS_12, OPS_13, OPS_14, OPS_15, OPS_16;

area C0`4,	ID;
area C6,	CHIPTYPE;
area C7.0`2,	FOSC;
area C7.2,	WDTE;
area C7.3,	PWRTE;
area C7.4,	FOSC2;
area C7.5,	MCLRE;
area C7.6,	BODEN;
area C7.7,	LVP;
area C7.8,	CPD;
area C7.9,	_undefC7_9;
area C7.10`4,	CP;

// default config
init FOSC := FOSC1_INT;		// internal osc
init WDTE := 0;			// WDT disabled
init PWRTE := 0;		// PWRT enabled
init FOSC2 := 1;		// internal osc
init MCLRE := 0;		// no MCLR pin
init BODEN := 0;		// BOD disabled
init LVP := 0;			// LVP disabled
init CPD := 1;			// no eeprom protection
init _undefC7_9 := 1;		// undefined, but must be set
init CP := 0b1111;		// no code protection

// Any bank
area R0x00,	INDF;
area R0x02,	PCL;
area R0x03,	STATUS;
area		STATUS.0,	C, DC, Z, PD, TO;
area		STATUS.5`2,	RP;
area		STATUS.7,	IRP;
area R0x04,	FSR;
area R0x0a,	PCLATH;
area R0x0b,	INTCON;
area		INTCON.0,	RBIF, INTF, T0IF, RBIE, INTE, T0IE, PEIE, GIE;
area R0x70`0x10,RAM;

// Bank 0 only
area R0x01,	TMR0;
area R0x05,	PORTA;
area R0x06,	PORTB;
area R0x0c,	PIR1;
area		PIR1.0,		T1IF, T2IF, CCP1IF, , TXIF, RCIF, CMIF, EEIF;
area R0x0e,	TMR1L;
area R0x0f,	TMR1H;
area R0x10,	T1CON;
area		T1CON.0,	TMR1ON,
				TMR1CS,
				T1SYNC,
				T1OSCEN;
area		T1CON.4`2,	T1CKPS;
area R0x11,	TMR2;
area R0x12,	T2CON;
area		T2CON.0`2,	T2CKPS;
area		T2CON.2,	TMR2ON;
area		T2CON.3`4,	TOUTPS;
area R0x15,	CCPR1L;
area R0x16,	CCPR1H;
area R0x17,	CCP1CON;
area 		CCP1CON.0`4,	CCP1M,
				CCP1Y,
				CCP1X;
area R0x18,	RCSTA;
area		RCSTA.0,	RX9D, OERR, FERR, ADEN, CREN, SREN, RX9, SPEN;
area R0x19,	TXREG;
area R0x1a,	RCREG;
area R0x1f,	CMCON;
area		CMCON.0`3,	CM;
area		CMCON.3,	CIS;
area		CMCON.4,	C1INV;
area		CMCON.5,	C2INV;
area		CMCON.6,	C1OUT;
area		CMCON.7,	C2OUT;
area R0x20`0x50,RAM0;

// Bank 1 only
area R0x01,	OPTION;
area		OPTION.0`3,	PS;
area		OPTION.3,	PSA, T0SE, T0CS, INTEDG, RBPU;
area R0x05,	TRISA;
area R0x06,	TRISB;
area R0x0c,	PIE1;
area		PIE1.0,		T1IE, T2IE, CCP1IE, , TXIE, RCIE, CMIE, EEIE;
area R0x0e,	PCON;
area		PCON.0,		BOD, POR, , OSCF;
area R0x12,	PR2;
area R0x18,	TXSTA;
area		TXSTA.0,	TX9D, TRMT, BRGH, , SYNC, TXEN, TX9, CSRC;
area R0x19,	SPBRG;
area R0x1a,	EEDATA;
area R0x1b,	EEADR;
area R0x1c,	EECON1;
area		EECON1.0,	RD, WR, WREN, WRERR;
area R0x1d,	EECON2;
area R0x1f,	VRCON;
area		VRCON.0`4,	VR;
area		VRCON.5,	VRR;
area		VRCON.6,	VROE;
area		VRCON.7,	VREN;
area R0x20`0x50,RAM1;

// Bank 2 only
area R0x20`0x30,RAM2;
