/*
 * Some handy 12F675 things
 *
 */
chip "12f675";
#include_only_once

#include <stdmac>
#include <tmr0ps>
#include <vref>

enum	FOSC_LP, FOSC_XT, FOSC_HS, FOSC_EC,
	FOSC_INT, FOSC_INT_O4, FOSC_RC, FOSC_RC_O4;

enum	PST0_2, PST0_4, PST0_8, PST0_16,
	PST0_32, PST0_64, PST0_128, PST0_256;

enum	PSWDT_1, PSWDT_2, PSWDT_4, PSWDT_8,
	PSWDT_16, PSWDT_32, PSWDT_64, PSWDT_128;

area C0`4,	ID;
area C6,	CHIPTYPE;
area C7.0`3,	FOSC := FOSC_INT;	// default internal osc
area C7.3,	WDTE := 0;		// default wdt disabled
area C7.4,	PWRTE := 0;		// default pwrt enabled
area C7.5,	MCLRE := 0;		// default no MCLR pin
area C7.6,	BODEN := 0;		// default BOD disabled
area C7.7,	CP := 1;		// default no protection
area C7.8,	CPD := 1;		// default no protection
area C7.12`2,	BG;			// no default

// Bank 0
area R0x00,	INDF;
area R0x01,	TMR0;
area R0x02,	PCL;
area R0x03,	STATUS;
area		STATUS.0,	C, DC, Z, PD, TO;
area		STATUS.5`2,	RP;
area		STATUS.7,	IRP;
area R0x04,	FSR;
area R0x05,	GPIO;
area R0x0a,	PCLATH;
area R0x0b,	INTCON;
area		INTCON.0,	GPIF, INTF, T0IF, GPIE, INTE, T0IE, PEIE, GIE;
area R0x0c,	PIR1;
area		PIR1.0,		T1IF, , , CMIF, , , ADIF, EEIF;
area R0x0e,	TMR1L;
area R0x0f,	TMR1H;
area R0x10,	T1CON;
area		T1CON.0,	TMR1ON,
				TMR1CS,
				T1SYNC,
				T1OSCEN;
area		T1CON.4`2,	T1CKPS;
area		T1CON.6,	TMR1GE;
area R0x19,	CMCON;
area		CMCON.0`3,	CM;
area		CMCON.3,	CIS;
area		CMCON.4,	CINV;
area		CMCON.6,	COUT;
area R0x1e,	ADRESH;
area R0x1f,	ADCON0;
area		ADCON0.0,	ADON,
				GO;
area		ADCON0.2`2,	CHS;
area		ADCON0.6,	VCFG,
				ADFM;

// Bank 1
area R0x01,	OPTION;
area		OPTION.0`3,	PS;
area		OPTION.3,	PSA, T0SE, T0CS, INTEDG, GPPU;
area R0x05,	TRISIO;
area R0x0c,	PIE1;
area		PIE1.0,		T1IE, , , CMIE, , , ADIE, EEIE;
area R0x0e,	PCON;
area		PCON.0,		BOD, POR;
area R0x10,	OSCCAL;
area		OSCCAL.2`6,	CAL;
area R0x15,	WPU;
area R0x16,	IOCB;
area R0x19,	VRCON;
area		VRCON.0`4,	VR;
area		VRCON.5,	VRR;
area		VRCON.7,	VREN;
area R0x1a,	EEDATA;
area R0x1b,	EEADR;
area R0x1c,	EECON1;
area		EECON1.0,	RD, WR, WREN, WRERR;
area R0x1d,	EECON2;
area R0x1e,	ADRESL;
area R0x1f,	ANSEL;
area		ANSEL.0`4,	ANS;
area		ANSEL.4`3,	ADCS;

