; *********************************************************************
;
;  DIVAPC ARM Assembler source
;
;  Sys.S.StdDefs  Standard definitions
;
;  Versions
;
;   8-1-92  INH  Derived from CPU.S.DEFS
;
; *********************************************************************

; Register numbers

R0  RN   0
R1  RN   1
R2  RN   2
R3  RN   3
R4  RN   4
R5  RN   5
R6  RN   6
R7  RN   7
R8  RN   8
R9  RN   9
R10 RN   10
R11 RN   11
R12 RN   12
R13 RN   13
R14 RN   14
PC  RN   15

r0  RN   0    ; or in little letters....:-)
r1  RN   1
r2  RN   2
r3  RN   3
r4  RN   4
r5  RN   5
r6  RN   6
r7  RN   7
r8  RN   8
r9  RN   9
r10 RN   10
r11 RN   11
r12 RN   12
r13 RN   13
r14 RN   14
pc  RN   15

; Register names for APCS

SL  RN   10
FP  RN   11
IP  RN   12
SP  RN   13
LR  RN   14

sl  RN   10
fp  RN   11
ip  RN   12
sp  RN   13
lr  RN   14


XOS_bit        EQU &20000

; SVC mode macro definitions

OS_EnterOS    EQU &16

        MACRO
$label  EnterSVCmode
$label  SWI OS_EnterOS                     ; SWI OS_EnterOS
        MEND

        MACRO
$label  ExitSVCmode
$label  TEQP    PC, #0               ; Clears all flags
        MOVNV   R0, R0
        MEND


 END
