; Generated by gcc 2.95.2 19991024 (release) for ARM/RISC OS
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	AREA |C$$code1|, CODE, READONLY
|gcc2_compiled.|
	EXPORT	|alloc_0|
	ALIGN
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	ALIGN
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	DCW	16
	DCW	-32767
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	3
	DCW	-3
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	16
	DCW	-32767
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	3
	DCW	-3
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	16
	DCW	-32767
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	3
	DCW	-3
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	16
	DCW	-32767
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	3
	DCW	-3
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	16
	DCW	-32767
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	16
	DCW	-32767
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	16
	DCW	-32767
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	16
	DCW	-32767
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	16
	DCW	-32767
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	16
	DCW	-32767
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	16
	DCW	-32767
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	16
	DCW	-32767
	EXPORT	|alloc_2|
	ALIGN
|alloc_2|
	DCW	4
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	8
	DCW	-127
	DCW	9
	DCW	-255
	DCW	10
	DCW	-511
	DCW	11
	DCW	-1023
	DCW	12
	DCW	-2047
	DCW	13
	DCW	-4095
	DCW	14
	DCW	-8191
	DCW	15
	DCW	-16383
	DCW	4
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	8
	DCW	-127
	DCW	9
	DCW	-255
	DCW	10
	DCW	-511
	DCW	11
	DCW	-1023
	DCW	12
	DCW	-2047
	DCW	13
	DCW	-4095
	DCW	14
	DCW	-8191
	DCW	15
	DCW	-16383
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	EXPORT	|alloc_3|
	ALIGN
|alloc_3|
	DCW	4
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	8
	DCW	-127
	DCW	9
	DCW	-255
	DCW	10
	DCW	-511
	DCW	11
	DCW	-1023
	DCW	12
	DCW	-2047
	DCW	13
	DCW	-4095
	DCW	14
	DCW	-8191
	DCW	15
	DCW	-16383
	DCW	4
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	8
	DCW	-127
	DCW	9
	DCW	-255
	DCW	10
	DCW	-511
	DCW	11
	DCW	-1023
	DCW	12
	DCW	-2047
	DCW	13
	DCW	-4095
	DCW	14
	DCW	-8191
	DCW	15
	DCW	-16383
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	EXPORT	|alloc_4|
	ALIGN
|alloc_4|
	DCW	4
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	3
	DCW	-3
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	8
	DCW	-127
	DCW	9
	DCW	-255
	DCW	10
	DCW	-511
	DCW	11
	DCW	-1023
	DCW	12
	DCW	-2047
	DCW	13
	DCW	-4095
	DCW	14
	DCW	-8191
	DCW	4
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	3
	DCW	-3
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	8
	DCW	-127
	DCW	9
	DCW	-255
	DCW	10
	DCW	-511
	DCW	11
	DCW	-1023
	DCW	12
	DCW	-2047
	DCW	13
	DCW	-4095
	DCW	14
	DCW	-8191
	DCW	4
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	3
	DCW	-3
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	8
	DCW	-127
	DCW	9
	DCW	-255
	DCW	10
	DCW	-511
	DCW	11
	DCW	-1023
	DCW	12
	DCW	-2047
	DCW	13
	DCW	-4095
	DCW	14
	DCW	-8191
	DCW	4
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	3
	DCW	-3
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	8
	DCW	-127
	DCW	9
	DCW	-255
	DCW	10
	DCW	-511
	DCW	11
	DCW	-1023
	DCW	12
	DCW	-2047
	DCW	13
	DCW	-4095
	DCW	14
	DCW	-8191
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	3
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	4
	DCW	-7
	DCW	5
	DCW	-15
	DCW	6
	DCW	-31
	DCW	7
	DCW	-63
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	DCW	2
	DCW	0
	DCW	5
	DCW	3
	DCW	7
	DCW	5
	DCW	10
	DCW	9
	AREA |C$$data1|, DATA
	ALIGN
|grp_3tab|
	KEEP |grp_3tab|
	DCD	0
	%	380
	ALIGN
|grp_5tab|
	KEEP |grp_5tab|
	DCD	0
	%	1532
	ALIGN
|grp_9tab|
	KEEP |grp_9tab|
	DCD	0
	%	12284
	AREA |C$$code2|, CODE, READONLY
	ALIGN
|mulmul.3|
	KEEP |mulmul.3|
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD &bfe55555, &55555555	; double -6.66666666666666629659e-1
	DCD &3fe55555, &55555555	; double 6.66666666666666629659e-1
	DCD &3fd24924, &92492492	; double 2.85714285714285698425e-1
	DCD &3fc11111, &11111111	; double 1.33333333333333331483e-1
	DCD &3fb08421, &8421084	; double 6.45161290322580627254e-2
	DCD &3fa04104, &10410410	; double 3.17460317460317442695e-2
	DCD &3f902040, &81020408	; double 1.57480314960629919074e-2
	DCD &3f801010, &10101010	; double 7.84313725490196067547e-3
	DCD &3f700804, &2010080	; double 3.91389432485322874555e-3
	DCD &3f600401, &401004	; double 1.95503421309872922607e-3
	DCD &3f500200, &40080100	; double 9.77039570102589127742e-4
	DCD &3f400100, &10010010	; double 4.88400488400488400065e-4
	DCD &3f300080, &4002001	; double 2.44170430960810645824e-4
	DCD &3f200040, &1000400	; double 1.22077763535372030290e-4
	DCD &3f100020, &400080	; double 6.10370189519943845413e-5
	DCD &3f000010, &100010	; double 3.05180437933928435171e-5
	DCD &bfe99999, &9999999a	; double -8.00000000000000044409e-1
	DCD &bfd99999, &9999999a	; double -4.00000000000000022204e-1
	DCD &3fd99999, &9999999a	; double 4.00000000000000022204e-1
	DCD &3fe99999, &9999999a	; double 8.00000000000000044409e-1
	DCD &bfec71c7, &1c71c71c	; double -8.88888888888888839546e-1
	DCD &bfdc71c7, &1c71c71c	; double -4.44444444444444419773e-1
	DCD &bfcc71c7, &1c71c71c	; double -2.22222222222222209886e-1
	DCD &3fcc71c7, &1c71c71c	; double 2.22222222222222209886e-1
	DCD &3fdc71c7, &1c71c71c	; double 4.44444444444444419773e-1
	DCD &3fec71c7, &1c71c71c	; double 8.88888888888888839546e-1
	ALIGN
|base.4|
	KEEP |base.4|
	DCD	1
	DCD	0
	DCD	2
	%	24
	DCD	17
	DCD	18
	DCD	0
	DCD	19
	DCD	20
	%	16
	DCD	21
	DCD	1
	DCD	22
	DCD	23
	DCD	0
	DCD	24
	DCD	25
	DCD	2
	DCD	26
	ALIGN
|tablen.5|
	KEEP |tablen.5|
	DCD	3
	DCD	5
	DCD	9
	AREA |C$$zidata1|,NOINIT
|itable.6|
	% 4	; size=4
	AREA |C$$data2|, DATA
	ALIGN
|tables.7|
	KEEP |tables.7|
	DCD	|grp_3tab|
	DCD	|grp_5tab|
	DCD	|grp_9tab|
	AREA |C$$code3|, CODE, READONLY
	ALIGN
	EXPORT	|init_layer2|
|init_layer2|
	; args = 0, pretend = 0, frame = 0, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	mov	__v4, #0
|L..6|
	ldr	__v5, |L..33|
	ldr	__a4, |L..33|+4
	ldr	__ip, |L..33|+8
	mov	__a3, __v4, asl #2
	ldr	__lr, [__ip, __a3]
	mov	__v3, #0
	ldr	__ip, [__a4, __a3]
	cmp	__v3, __lr
	str	__ip, [__v5, #0]
	bge	|L..5|
|L..10|
	mov	__v1, #0
	cmp	__v1, __lr
	bge	|L..9|
|L..14|
	mov	__v2, #0
	cmp	__v2, __lr
	bge	|L..13|
|L..18|
	add	__a3, __v4, __v4, asl #3
	ldr	__a1, [__v5, #0]
	mov	__a3, __a3, asl #2
	ldr	__a2, |L..33|+12
	add	__ip, __a3, __v2, asl #2
	ldr	__ip, [__a2, __ip]
	str	__ip, [__a1], #4
	add	__ip, __a3, __v1, asl #2
	ldr	__a4, [__a2, __ip]
	add	__a3, __a3, __v3, asl #2
	ldr	__a3, [__a2, __a3]
	str	__a1, [__v5, #0]
	mov	__ip, __a1
	str	__a4, [__ip], #4
	add	__v2, __v2, #1
	str	__ip, [__v5, #0]
	cmp	__v2, __lr
	str	__a3, [__a1, #4]
	add	__ip, __ip, #4
	str	__ip, [__v5, #0]
	blt	|L..18|
|L..13|
	add	__v1, __v1, #1
	cmp	__v1, __lr
	blt	|L..14|
|L..9|
	add	__v3, __v3, #1
	cmp	__v3, __lr
	blt	|L..10|
|L..5|
	add	__v4, __v4, #1
	cmp	__v4, #2
	ble	|L..6|
	mov	__v1, #0
|L..26|
	mov	__v3, #3
	ldr	__a3, |L..33|+16
	mov	__v4, #0
	ldr	__ip, |L..33|+20
	add	__v2, __a3, __v1, asl #9
	add	__ip, __ip, __v1, asl #3
	ldmia	__ip, {__v5-__v6}
|L..30|
	mov	__a1, __v3
	bl	|__floatsidf|
	adr	__a3, |L..33|+24
	ldmia	__a3, {__a3-__a4}
	add	__v4, __v4, #1
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..33|+32
	ldmia	__a1, {__a1-__a2}
	sub	__v3, __v3, #1
	bl	|pow|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__muldf3|
	cmp	__v4, #62
	stmia	__v2!, {__a1-__a2}
	ble	|L..30|
	add	__v1, __v1, #1
	adr	__a3, |L..33|+40
	ldmia	__a3, {__a3-__a4}
	cmp	__v1, #26
	stmia	__v2, {__a3-__a4}
	ble	|L..26|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..34|
	ALIGN
|L..33|
	DCD	|itable.6|
	DCD	|tables.7|
	DCD	|tablen.5|
	DCD	|base.4|
	DCD	|muls|
	DCD	|mulmul.3|
	DCD &3fd55555, &55555555	; double 3.33333333333333314830e-1
	DCD &40000000, &0	; double 2.00000000000000000000e0
	DCD &0, &0	; double 0.00000000000000000000e0
	AREA |C$$zidata2|,NOINIT
|scfsi_buf.11|
	% 256	; size=256
	AREA |C$$code4|, CODE, READONLY
	ALIGN
	EXPORT	|II_step_one|
|II_step_one|
	; args = 0, pretend = 0, frame = 12, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #12
	stmia	__sp, {__a1, __a2}	; phole stm
	ldr	__ip, [__a3, #0]
	ldr	__v4, [__a3, #76]
	ldr	__v3, [__a3, #72]
	sub	__ip, __ip, #1
	cmp	__ip, #0
	mov	__ip, __v3, asl __ip
	str	__ip, [__sp, #8]
	mov	__v6, __a1
	ldr	__v5, [__a3, #4]
	beq	|L..36|
	subs	__v2, __v5, #0
	beq	|L..38|
|L..40|
	ldr	__ip, [__v4, #2]	; load-rotate
	mov	__v1, __ip, asr #16
	mov	__a1, __v1
	bl	|getbits|
	mov	__ip, __a1
	mov	__a1, __v1
	and	__ip, __ip, #255
	str	__ip, [__v6], #4
	bl	|getbits|
	mov	__ip, #4
	add	__v4, __v4, __ip, asl __v1
	subs	__v2, __v2, #1
	and	__a1, __a1, #255
	str	__a1, [__v6], #4
	bne	|L..40|
|L..38|
	subs	__v2, __v3, __v5
	beq	|L..43|
|L..45|
	ldr	__ip, [__v4, #2]	; load-rotate
	mov	__v1, __ip, asr #16
	mov	__a1, __v1
	bl	|getbits|
	and	__a1, __a1, #255
	str	__a1, [__v6, #0]
	str	__a1, [__v6, #4]
	add	__v6, __v6, #8
	mov	__ip, #4
	add	__v4, __v4, __ip, asl __v1
	subs	__v2, __v2, #1
	bne	|L..45|
|L..43|
	ldr	__v6, [__sp, #0]
	ldr	__v2, [__sp, #8]
	ldr	__v1, |L..79|
	cmp	__v2, #0
	beq	|L..53|
|L..50|
	ldr	__ip, [__v6], #4
	cmp	__ip, #0
	beq	|L..49|
	mov	__a1, #2
	bl	|getbits_fast|
	and	__a1, __a1, #255
	str	__a1, [__v1], #4
|L..49|
	subs	__v2, __v2, #1
	bne	|L..50|
	b	|L..53|
|L..36|
	subs	__v2, __v3, #0
	beq	|L..55|
|L..57|
	ldr	__ip, [__v4, #2]	; load-rotate
	mov	__v1, __ip, asr #16
	mov	__a1, __v1
	bl	|getbits|
	mov	__ip, #4
	add	__v4, __v4, __ip, asl __v1
	subs	__v2, __v2, #1
	and	__a1, __a1, #255
	str	__a1, [__v6], #4
	bne	|L..57|
|L..55|
	ldr	__v6, [__sp, #0]
	subs	__v2, __v3, #0
	ldr	__v1, |L..79|
	beq	|L..53|
|L..62|
	ldr	__ip, [__v6], #4
	cmp	__ip, #0
	beq	|L..61|
	mov	__a1, #2
	bl	|getbits_fast|
	and	__a1, __a1, #255
	str	__a1, [__v1], #4
|L..61|
	subs	__v2, __v2, #1
	bne	|L..62|
|L..53|
	ldr	__v6, [__sp, #0]
	ldr	__v2, [__sp, #8]
	ldr	__v1, |L..79|
	cmp	__v2, #0
	beq	|L..66|
|L..68|
	ldr	__ip, [__v6], #4
	cmp	__ip, #0
	beq	|L..67|
	ldr	__ip, [__v1], #4
	cmp	__ip, #1
	beq	|L..72|
	bcc	|L..71|
	cmp	__ip, #2
	beq	|L..73|
	b	|L..74|
|L..71|
	mov	__a1, #6
	bl	|getbits_fast|
	ldr	__a3, [__sp, #4]
	str	__a1, [__a3], #4
	mov	__a1, #6
	str	__a3, [__sp, #4]
	bl	|getbits_fast|
	ldr	__ip, [__sp, #4]
	str	__a1, [__ip], #4
	mov	__a1, #6
	str	__ip, [__sp, #4]
	bl	|getbits_fast|
	ldr	__a3, [__sp, #4]
	str	__a1, [__a3], #4
	b	|L..77|
|L..72|
	mov	__a1, #6
	bl	|getbits_fast|
	ldr	__a3, [__sp, #4]
	mov	__ip, __a1
	str	__ip, [__a3], #4
	str	__ip, [__a3], #4
	mov	__a1, #6
	str	__a3, [__sp, #4]
	bl	|getbits_fast|
	ldr	__ip, [__sp, #4]
	str	__a1, [__ip], #4
	str	__ip, [__sp, #4]
	b	|L..67|
|L..73|
	mov	__a1, #6
	bl	|getbits_fast|
	ldr	__a3, [__sp, #4]
	mov	__ip, __a1
	str	__ip, [__a3], #4
	b	|L..78|
|L..74|
	mov	__a1, #6
	bl	|getbits_fast|
	ldr	__ip, [__sp, #4]
	str	__a1, [__ip], #4
	mov	__a1, #6
	str	__ip, [__sp, #4]
	bl	|getbits_fast|
	ldr	__a3, [__sp, #4]
	mov	__ip, __a1
|L..78|
	str	__ip, [__a3], #4
	str	__ip, [__a3], #4
|L..77|
	str	__a3, [__sp, #4]
|L..67|
	subs	__v2, __v2, #1
	bne	|L..68|
|L..66|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..80|
	ALIGN
|L..79|
	DCD	|scfsi_buf.11|
	AREA |C$$data3|, DATA
	ALIGN
|table.15|
	KEEP |table.15|
	DCD	0
	DCD	0
	DCD	0
	DCD	|grp_3tab|
	DCD	0
	DCD	|grp_5tab|
	DCD	0
	DCD	0
	DCD	0
	DCD	|grp_9tab|
	ALIGN
|table.16|
	KEEP |table.16|
	DCD	0
	DCD	0
	DCD	0
	DCD	|grp_3tab|
	DCD	0
	DCD	|grp_5tab|
	DCD	0
	DCD	0
	DCD	0
	DCD	|grp_9tab|
	AREA |C$$code5|, CODE, READONLY
	ALIGN
	EXPORT	|II_step_two|
|II_step_two|
	; args = 4, pretend = 0, frame = 48, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #48
	str	__a3, [__sp, #4]
	ldr	__a3, [__a4, #76]
	str	__a1, [__sp, #28]
	str	__a3, [__sp, #24]
	ldr	__v1, [__a4, #4]
	mov	__ip, #0
	str	__ip, [__sp, #8]
	str	__v1, [__sp, #20]
	ldr	__lr, [__a4, #0]
	str	__a2, [__sp, #0]
	str	__lr, [__sp, #12]
	ldr	__a4, [__a4, #72]
	cmp	__ip, __v1
	str	__a4, [__sp, #16]
	bge	|L..83|
|L..85|
	ldr	__a1, [__sp, #24]
	ldr	__a2, [__sp, #12]
	mov	__v5, #0
	ldr	__ip, [__a1, #2]	; load-rotate
	cmp	__v5, __a2
	mov	__ip, __ip, asr #16
	str	__ip, [__sp, #32]
	bge	|L..84|
|L..89|
	ldr	__a4, [__sp, #28]
	ldr	__a3, [__a4], #4
	cmp	__a3, #0
	str	__a4, [__sp, #28]
	beq	|L..90|
	ldr	__v1, [__sp, #24]
	mov	__ip, __a3, asl #2
	ldr	__a3, [__v1, __ip]	; movhi
	ldr	__ip, [__v1, __ip]
	mov	__a3, __a3, asl #16
	mov	__v4, __a3, asr #16
	movs	__v6, __ip, asr #16
	bpl	|L..91|
	ldr	__ip, [__fp, #4]
	ldr	__lr, [__sp, #4]
	ldr	__a3, |L..115|
	mov	__a1, __v4
	ldr	__a4, [__lr, __ip, asl #2]
	mov	__ip, __v4, asl #9
	add	__ip, __ip, __a4, asl #3
	add	__ip, __ip, __a3
	ldmia	__ip, {__v2-__v3}
	bl	|getbits|
	ldr	__a2, [__sp, #0]
	add	__a1, __a1, __v6
	ldr	__a3, [__sp, #8]
	add	__v1, __a2, __v5, asl #10
	add	__v1, __v1, __a3, asl #3
	bl	|__floatsidf|
	mov	__a4, __v3
	mov	__a3, __v2
	bl	|__muldf3|
	stmia	__v1, {__a1-__a2}
	mov	__a1, __v4
	bl	|getbits|
	add	__a1, __a1, __v6
	bl	|__floatsidf|
	mov	__a4, __v3
	mov	__a3, __v2
	bl	|__muldf3|
	add	__ip, __v1, #256
	stmia	__ip, {__a1-__a2}
	mov	__a1, __v4
	bl	|getbits|
	add	__a1, __a1, __v6
	bl	|__floatsidf|
	mov	__a4, __v3
	mov	__a3, __v2
	bl	|__muldf3|
	add	__v1, __v1, #512
	stmia	__v1, {__a1-__a2}
	b	|L..92|
|L..91|
	ldr	__a4, [__fp, #4]
	ldr	__ip, [__sp, #4]
	mov	__a1, __v4
	ldr	__v1, [__ip, __a4, asl #2]
	bl	|getbits|
	ldr	__ip, |L..115|+4
	ldr	__lr, [__sp, #0]
	mov	__a1, __a1, asl #2
	ldr	__a2, [__sp, #8]
	add	__a3, __lr, __v5, asl #10
	ldr	__ip, [__ip, __v6, asl #2]
	add	__a3, __a3, __a2, asl #3
	add	__ip, __ip, __a1, asl #1
	add	__a4, __ip, __a1
	ldr	__ip, [__ip, __a1]
	mov	__v1, __v1, asl #3
	ldr	__lr, |L..115|
	add	__ip, __v1, __ip, asl #9
	add	__ip, __ip, __lr
	ldmia	__ip, {__a1-__a2}
	stmia	__a3, {__a1-__a2}
	add	__a4, __a4, #4
	ldr	__ip, [__a4], #4
	add	__ip, __v1, __ip, asl #9
	add	__ip, __ip, __lr
	ldmia	__ip, {__a1-__a2}
	add	__v2, __a3, #256
	stmia	__v2, {__a1-__a2}
	ldr	__ip, [__a4, #0]
	add	__v1, __v1, __ip, asl #9
	add	__ip, __v1, __lr
	ldmia	__ip, {__a4-__v1}
	add	__a3, __a3, #512
	stmia	__a3, {__a4-__v1}
|L..92|
	ldr	__v1, [__sp, #4]
	add	__v1, __v1, #12
	str	__v1, [__sp, #4]
	b	|L..88|
|L..90|
	ldr	__ip, [__sp, #0]
	ldr	__lr, [__sp, #8]
	adr	__a3, |L..115|+8
	ldmia	__a3, {__a3-__a4}
	add	__a2, __ip, __v5, asl #10
	add	__a2, __a2, __lr, asl #3
	add	__ip, __a2, #512
	stmia	__ip, {__a3-__a4}
	add	__ip, __a2, #256
	stmia	__ip, {__a3-__a4}
	stmia	__a2, {__a3-__a4}
|L..88|
	ldr	__a1, [__sp, #12]
	add	__v5, __v5, #1
	cmp	__v5, __a1
	blt	|L..89|
|L..84|
	ldr	__a2, [__sp, #8]
	ldr	__a3, [__sp, #24]
	ldr	__a4, [__sp, #32]
	mov	__ip, #4
	ldr	__v1, [__sp, #20]
	add	__a2, __a2, #1
	add	__a3, __a3, __ip, asl __a4
	str	__a2, [__sp, #8]
	cmp	__a2, __v1
	str	__a3, [__sp, #24]
	blt	|L..85|
|L..83|
	ldr	__ip, [__sp, #20]
	ldr	__lr, [__sp, #16]
	str	__ip, [__sp, #8]
	cmp	__ip, __lr
	bge	|L..97|
|L..99|
	ldr	__a1, [__sp, #24]
	ldr	__a2, [__sp, #28]
	ldr	__ip, [__a1, #2]	; load-rotate
	add	__a2, __a2, #4
	ldr	__a3, [__a2], #4
	mov	__ip, __ip, asr #16
	str	__a2, [__sp, #28]
	cmp	__a3, #0
	str	__ip, [__sp, #32]
	beq	|L..100|
	mov	__ip, __a3, asl #2
	ldr	__a3, [__a1, __ip]	; movhi
	ldr	__ip, [__a1, __ip]
	mov	__a3, __a3, asl #16
	mov	__v4, __a3, asr #16
	movs	__v6, __ip, asr #16
	bpl	|L..101|
	ldr	__a3, [__sp, #4]
	ldr	__a4, [__fp, #4]
	mov	__a1, __v4
	add	__ip, __a3, __a4, asl #2
	ldr	__ip, [__ip, #12]
	mov	__v5, __v4, asl #9
	ldr	__v1, |L..115|
	add	__ip, __v5, __ip, asl #3
	add	__ip, __ip, __v1
	ldmia	__ip, {__a3-__a4}
	add	__v1, __sp, #32
	stmib	__v1, {__a3-__a4}
	bl	|getbits|
	add	__a1, __a1, __v6
	bl	|__floatsidf|
	ldr	__ip, [__sp, #0]
	ldr	__lr, [__sp, #8]
	mov	__a4, __a2
	mov	__a3, __a1
	add	__v3, __ip, __lr, asl #3
	stmia	__v3, {__a3-__a4}
	add	__v1, __sp, #32
	ldmib	__v1, {__a3-__a4}
	bl	|__muldf3|
	add	__ip, __v3, #1024
	stmia	__ip, {__a1-__a2}
	mov	__a1, __v4
	bl	|getbits|
	add	__a1, __a1, __v6
	bl	|__floatsidf|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__ip, __sp, #32
	ldmib	__ip, {__a3-__a4}
	add	__lr, __v3, #256
	str	__lr, [__sp, #44]
	stmia	__lr, {__v1-__v2}
	bl	|__muldf3|
	add	__ip, __v3, #1280
	stmia	__ip, {__a1-__a2}
	mov	__a1, __v4
	bl	|getbits|
	add	__a1, __a1, __v6
	bl	|__floatsidf|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__ip, __sp, #32
	ldmib	__ip, {__a3-__a4}
	add	__v4, __v3, #512
	stmia	__v4, {__v1-__v2}
	bl	|__muldf3|
	add	__ip, __v3, #1536
	stmia	__ip, {__a1-__a2}
	ldr	__lr, [__fp, #4]
	ldr	__a1, [__sp, #4]
	ldr	__ip, [__a1, __lr, asl #2]
	ldr	__a2, |L..115|
	add	__v5, __v5, __ip, asl #3
	add	__v5, __v5, __a2
	ldmia	__v5, {__a3-__a4}
	add	__v1, __sp, #32
	stmib	__v1, {__a3-__a4}
	ldmia	__v3, {__a1-__a2}
	bl	|__muldf3|
	stmia	__v3, {__a1-__a2}
	ldr	__ip, [__sp, #44]
	ldmia	__ip, {__a1-__a2}
	add	__lr, __sp, #32
	ldmib	__lr, {__a3-__a4}
	bl	|__muldf3|
	ldr	__a3, [__sp, #44]
	stmia	__a3, {__a1-__a2}
	ldmia	__v4, {__a1-__a2}
	add	__v1, __sp, #32
	ldmib	__v1, {__a3-__a4}
	bl	|__muldf3|
	stmia	__v4, {__a1-__a2}
	b	|L..102|
|L..116|
	ALIGN
|L..115|
	DCD	|muls|
	DCD	|table.15|
	DCD &0, &0	; double 0.00000000000000000000e0
|L..101|
	ldr	__ip, [__fp, #4]
	ldr	__lr, [__sp, #4]
	mov	__a1, __v4
	ldr	__v1, [__lr, __ip, asl #2]
	add	__ip, __lr, __ip, asl #2
	ldr	__v2, [__ip, #12]
	bl	|getbits|
	ldr	__ip, |L..117|
	ldr	__a2, [__sp, #0]
	ldr	__a4, [__sp, #8]
	mov	__a1, __a1, asl #2
	ldr	__a3, [__ip, __v6, asl #2]
	add	__v6, __a2, __a4, asl #3
	add	__a3, __a3, __a1, asl #1
	ldr	__ip, [__a3, __a1]
	mov	__v4, __v1, asl #3
	ldr	__v1, |L..117|+4
	add	__ip, __v4, __ip, asl #9
	add	__ip, __ip, __v1
	ldmia	__ip, {__a4-__v1}
	stmia	__v6, {__a4-__v1}
	mov	__v2, __v2, asl #3
	ldr	__ip, [__a3, __a1]
	add	__v3, __a3, __a1
	ldr	__v1, |L..117|+4
	add	__ip, __v2, __ip, asl #9
	add	__ip, __ip, __v1
	ldmia	__ip, {__a1-__a2}
	add	__lr, __v6, #1024
	stmia	__lr, {__a1-__a2}
	ldr	__ip, [__v3, #4]!
	add	__ip, __v4, __ip, asl #9
	add	__ip, __ip, __v1
	ldmia	__ip, {__a2-__a3}
	add	__a1, __v6, #256
	stmia	__a1, {__a2-__a3}
	ldr	__ip, [__v3, #0]
	add	__ip, __v2, __ip, asl #9
	add	__ip, __ip, __v1
	ldmia	__ip, {__a3-__a4}
	add	__a1, __v6, #1280
	stmia	__a1, {__a3-__a4}
	ldr	__ip, [__v3, #4]!
	ldr	__a4, |L..117|+4
	add	__v1, __v4, __ip, asl #9
	add	__a1, __v1, __a4
	ldmia	__a1, {__a4-__v1}
	add	__a3, __v6, #512
	stmia	__a3, {__a4-__v1}
	ldr	__ip, [__v3, #0]
	ldr	__v1, |L..117|+4
	add	__v2, __v2, __ip, asl #9
	add	__v2, __v2, __v1
	ldmia	__v2, {__a1-__a2}
	add	__a4, __v6, #1536
	stmia	__a4, {__a1-__a2}
|L..102|
	ldr	__a2, [__sp, #4]
	add	__a2, __a2, #24
	str	__a2, [__sp, #4]
	b	|L..98|
|L..100|
	ldr	__a3, [__sp, #0]
	ldr	__a4, [__sp, #8]
	add	__a2, __a3, __a4, asl #3
	adr	__a3, |L..117|+8
	ldmia	__a3, {__a3-__a4}
	add	__ip, __a2, #1536
	stmia	__ip, {__a3-__a4}
	add	__ip, __a2, #1280
	stmia	__ip, {__a3-__a4}
	add	__ip, __a2, #1024
	stmia	__ip, {__a3-__a4}
	add	__ip, __a2, #512
	stmia	__ip, {__a3-__a4}
	add	__ip, __a2, #256
	stmia	__ip, {__a3-__a4}
	stmia	__a2, {__a3-__a4}
|L..98|
	ldr	__v1, [__sp, #8]
	ldr	__lr, [__sp, #24]
	ldr	__a1, [__sp, #32]
	mov	__ip, #4
	ldr	__a2, [__sp, #16]
	add	__v1, __v1, #1
	add	__lr, __lr, __ip, asl __a1
	str	__v1, [__sp, #8]
	cmp	__v1, __a2
	str	__lr, [__sp, #24]
	blt	|L..99|
|L..97|
	ldr	__a3, [__sp, #16]
	str	__a3, [__sp, #8]
	cmp	__a3, #31
	bgt	|L..106|
|L..108|
	ldr	__a4, [__sp, #12]
	mov	__v5, #0
	cmp	__v5, __a4
	bge	|L..107|
|L..112|
	ldr	__v1, [__sp, #0]
	ldr	__ip, [__sp, #8]
	adr	__a3, |L..117|+8
	ldmia	__a3, {__a3-__a4}
	add	__a2, __v1, __v5, asl #10
	add	__a2, __a2, __ip, asl #3
	add	__ip, __a2, #512
	stmia	__ip, {__a3-__a4}
	add	__ip, __a2, #256
	stmia	__ip, {__a3-__a4}
	ldr	__lr, [__sp, #12]
	add	__v5, __v5, #1
	stmia	__a2, {__a3-__a4}
	cmp	__v5, __lr
	blt	|L..112|
|L..107|
	ldr	__a1, [__sp, #8]
	add	__a1, __a1, #1
	cmp	__a1, #31
	str	__a1, [__sp, #8]
	ble	|L..108|
|L..106|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..118|
	ALIGN
|L..117|
	DCD	|table.16|
	DCD	|muls|
	DCD &0, &0	; double 0.00000000000000000000e0
	ALIGN
|translate.20|
	KEEP |translate.20|
	DCD	0
	DCD	2
	DCD	2
	DCD	2
	DCD	2
	DCD	2
	DCD	2
	DCD	0
	DCD	0
	DCD	0
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	0
	DCD	0
	DCD	2
	DCD	2
	DCD	0
	DCD	0
	DCD	0
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	0
	DCD	0
	DCD	2
	DCD	2
	DCD	2
	DCD	2
	DCD	2
	DCD	2
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	2
	DCD	2
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	3
	DCD	3
	DCD	3
	DCD	3
	DCD	3
	DCD	3
	DCD	0
	DCD	0
	DCD	0
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	0
	DCD	0
	DCD	3
	DCD	3
	DCD	0
	DCD	0
	DCD	0
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	0
	AREA |C$$data4|, DATA
	ALIGN
|tables.21|
	KEEP |tables.21|
	DCD	|alloc_0|
	DCD	|alloc_1|
	DCD	|alloc_2|
	DCD	|alloc_3|
	DCD	|alloc_4|
	AREA |C$$code6|, CODE, READONLY
	ALIGN
|sblims.22|
	KEEP |sblims.22|
	DCD	27
	DCD	30
	DCD	8
	DCD	12
	DCD	30
	ALIGN
|II_select_table|
	KEEP |II_select_table|
	; args = 0, pretend = 0, frame = 0, alloca = 0
	; frame_needed = 0, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	ldr	__ip, [__a1, #12]
	cmp	__ip, #0
	movne	__a3, #4
	bne	|L..121|
|L..120|
	ldr	__ip, [__a1, #0]
	ldr	__a3, [__a1, #32]
	ldr	__a4, [__a1, #36]
	rsb	__ip, __ip, #2
	mov	__ip, __ip, asl #6
	add	__ip, __ip, __a3, asl #2
	ldr	__a3, |L..122|
	add	__ip, __ip, __a4, asl #7
	ldr	__a3, [__a3, __ip]
|L..121|
	ldr	__ip, |L..122|+4
	mov	__a3, __a3, asl #2
	ldr	__ip, [__ip, __a3]
	str	__ip, [__a1, #76]
	ldr	__ip, |L..122|+8
	ldr	__ip, [__ip, __a3]
	str	__ip, [__a1, #72]
	mov	__pc, __lr
|L..123|
	ALIGN
|L..122|
	DCD	|translate.20|
	DCD	|tables.21|
	DCD	|sblims.22|
	ALIGN
	EXPORT	|do_layer2|
|do_layer2|
	; args = 0, pretend = 0, frame = 3104, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	sub	__ip, __sp, #3104
	cmp	__ip, __sl
	bllt	|__rt_stkovf_split_big|
	sub	__sp, __sp, #3104
	str	__a1, [__sp, #3080]
	ldr	__ip, [__sp, #3080]
	add	__v3, __a1, #60
	ldr	__a4, [__v3, #8]
	str	__a2, [__sp, #3084]
	str	__a3, [__sp, #3088]
	str	__a4, [__sp, #3100]
	mov	__a1, __v3
	ldr	__v1, [__ip, #60]
	bl	|II_select_table|
	ldr	__ip, [__v3, #48]
	mov	__v5, #0
	cmp	__ip, #1
	ldreq	__ip, [__v3, #52]
	moveq	__ip, __ip, asl #2
	addeq	__ip, __ip, #4
|L..125|
	ldrne	__ip, [__v3, #72]
|L..126|
	add	__v6, __sp, #2048
	add	__v6, __v6, #4
	add	__v4, __sp, #2304
	add	__v4, __v4, #4
	mov	__a1, __v6
	ldr	__lr, [__sp, #3100]
	mov	__a2, __v4
	cmp	__lr, #3
	cmpne	__v1, #1
	moveq	__lr, #0
	str	__lr, [__sp, #3100]
	mov	__a3, __v3
	str	__ip, [__v3, #4]
	bl	|II_step_one|
	mov	__a3, #0
	str	__a3, [__sp, #3092]
|L..131|
	mov	__a1, __v6
	add	__a2, __sp, #4
	mov	__a3, __v4
	ldr	__lr, [__sp, #3092]
	mov	__a4, __v3
	mov	__ip, __lr, asr #2
	str	__ip, [__sp, #0]
	bl	|II_step_two|
	mov	__a3, #0
	str	__a3, [__sp, #3096]
|L..135|
	ldr	__a4, [__sp, #3100]
	cmp	__a4, #0
	blt	|L..136|
	ldr	__a1, [__sp, #3080]
	ldr	__ip, [__sp, #3096]
	add	__a2, __sp, #4
	ldr	__a3, [__sp, #3084]
	add	__a2, __a2, __a4, asl #10
	ldr	__a4, [__sp, #3088]
	add	__a2, __a2, __ip, asl #8
	bl	|synth_1to1_mono|
	b	|L..140|
|L..136|
	ldr	__a1, [__sp, #3080]
	add	__ip, __sp, #3072
	ldr	__lr, [__sp, #3096]
	add	__ip, __ip, #4
	str	__ip, [__sp, #0]
	add	__v2, __sp, #4
	ldr	__a4, [__sp, #3088]
	mov	__a3, #0
	ldr	__ip, [__a4, #0]
	mov	__v1, __lr, asl #8
	ldr	__a4, [__sp, #3084]
	add	__a2, __v2, __v1
	str	__ip, [__sp, #3076]
	bl	|synth_1to1|
	add	__v5, __v5, __a1
	ldr	__a1, [__sp, #3080]
	add	__v1, __v1, #1024
	ldr	__a4, [__sp, #3084]
	add	__a2, __v2, __v1
	ldr	__ip, [__sp, #3088]
	mov	__a3, #1
	str	__ip, [__sp, #0]
	bl	|synth_1to1|
|L..140|
	add	__v5, __v5, __a1
	ldr	__lr, [__sp, #3096]
	add	__lr, __lr, #1
	cmp	__lr, #2
	str	__lr, [__sp, #3096]
	ble	|L..135|
	ldr	__a3, [__sp, #3092]
	add	__a3, __a3, #1
	cmp	__a3, #11
	str	__a3, [__sp, #3092]
	ble	|L..131|
	mov	__a1, __v5
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
	END
