; Generated by gcc 2.95.2 19991024 (release) for ARM/RISC OS
__r0	RN	0
__a1	RN	0
__a2	RN	1
__a3	RN	2
__a4	RN	3
__v1	RN	4
__v2	RN	5
__v3	RN	6
__v4	RN	7
__v5	RN	8
__v6	RN	9
__sl	RN	10
__fp	RN	11
__ip	RN	12
__sp	RN	13
__lr	RN	14
__pc	RN	15
__f0	FN	0
__f1	FN	1
__f2	FN	2
__f3	FN	3
__f4	FN	4
__f5	FN	5
__f6	FN	6
__f7	FN	7
	AREA |C$$code1|, CODE, READONLY
|gcc2_compiled.|
	ALIGN
|step.6|
	KEEP |step.6|
	DCD	2
	ALIGN
	EXPORT	|synth_1to1|
|synth_1to1|
	; args = 4, pretend = 0, frame = 12, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #12
	mov	__ip, #0
	str	__ip, [__sp, #0]
	cmp	__a3, #0
	ldr	__ip, [__fp, #4]
	mov	__v3, __a1
	ldr	__lr, [__ip, #0]
	mov	__a3, __a2
	ldr	__ip, |L..45|
	add	__v6, __a4, __lr
	ldr	__v1, [__v3, __ip]
	bne	|L..9|
	sub	__v1, __v1, #1
	and	__v1, __v1, #15
	add	__ip, __v3, #23040
	b	|L..41|
|L..9|
	add	__v6, __v6, #2
	add	__ip, __v3, #27392
|L..41|
	add	__ip, __ip, #164
	tst	__v1, #1
	beq	|L..11|
	mov	__v5, __ip
	mov	__v2, __v1
	add	__a1, __v2, #1
	and	__a1, __a1, #15
	mov	__a1, __a1, asl #3
	add	__a1, __a1, #2176
	add	__a1, __v5, __a1
	add	__a2, __v5, __v2, asl #3
	bl	|dct64|
	b	|L..12|
|L..46|
	ALIGN
|L..45|
	DCD	31908
|L..11|
	add	__v5, __ip, #2176
	add	__v2, __v1, #1
	mov	__a2, __v1, asl #3
	add	__a1, __ip, __a2
	add	__a2, __a2, __ip
	add	__a2, __a2, #2176
	add	__a2, __a2, #8
	bl	|dct64|
|L..12|
	mov	__a3, #16
	str	__a3, [__sp, #4]
	ldr	__a3, |L..48|
	mov	__ip, __v2, asl #4
	str	__ip, [__sp, #8]
	ldr	__ip, |L..48|+4
	sub	__v4, __a3, __v2, asl #3
	str	__v1, [__v3, __ip]
|L..16|
	ldmia	__v4, {__a1-__a2}
	ldmia	__v5, {__a3-__a4}
	bl	|__muldf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #8
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #16
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__adddf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #24
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #32
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__adddf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #40
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #48
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__adddf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #56
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #64
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__adddf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #72
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #80
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__adddf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #88
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #96
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__adddf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #104
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #112
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__adddf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__v1, #120
	add	__ip, __v4, __v1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, __v1
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	adr	__a3, |L..48|+8
	ldmia	__a3, {__a3-__a4}
	bl	|__gtdf2|
	cmp	__a1, #0
	ble	|L..17|
	ldr	__a3, [__sp, #0]
	add	__a3, __a3, #1
	str	__a3, [__sp, #0]
	mov	__ip, #255
	strb	__ip, [__v6, #0]
	mov	__a3, #127
	b	|L..47|
|L..49|
	ALIGN
|L..48|
	DCD	|decwin|+128
	DCD	31908
	DCD &40dfffc0, &0	; double 3.27670000000000000000e4
|L..47|
	strb	__a3, [__v6, #1]
	b	|L..15|
|L..17|
	adr	__a3, |L..50|
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__ltdf2|
	cmp	__a1, #0
	bge	|L..19|
	ldr	__ip, [__sp, #0]
	add	__ip, __ip, #1
	str	__ip, [__sp, #0]
	mov	__ip, #0
	strb	__ip, [__v6, #0]
	mov	__a3, #128
	strb	__a3, [__v6, #1]
	b	|L..15|
|L..19|
	adr	__a3, |L..50|+8
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__gtdf2|
	cmp	__a1, #0
	ble	|L..21|
	adr	__a3, |L..50|+16
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__adddf3|
	b	|L..42|
|L..21|
	adr	__a3, |L..50|+16
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
|L..42|
	bl	|__fixdfsi|
	strb	__a1, [__v6, #0]
	mov	__a1, __a1, asr #8
	strb	__a1, [__v6, #1]
|L..15|
	add	__v5, __v5, #128
	add	__v4, __v4, #256
	ldr	__a3, [__sp, #4]
	add	__v6, __v6, #4
	subs	__a3, __a3, #1
	str	__a3, [__sp, #4]
	bne	|L..16|
	ldmia	__v4, {__a1-__a2}
	ldmia	__v5, {__a3-__a4}
	bl	|__muldf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__ip, #16
	add	__a3, __v4, __ip
	ldmia	__a3, {__a1-__a2}
	add	__ip, __v5, __ip
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__ip, #32
	add	__a3, __v4, __ip
	ldmia	__a3, {__a1-__a2}
	add	__ip, __v5, __ip
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__ip, #48
	add	__a3, __v4, __ip
	ldmia	__a3, {__a1-__a2}
	add	__ip, __v5, __ip
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__ip, #64
	add	__a3, __v4, __ip
	ldmia	__a3, {__a1-__a2}
	add	__ip, __v5, __ip
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__ip, #80
	add	__a3, __v4, __ip
	ldmia	__a3, {__a1-__a2}
	add	__ip, __v5, __ip
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__ip, #96
	add	__a3, __v4, __ip
	ldmia	__a3, {__a1-__a2}
	add	__ip, __v5, __ip
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__ip, #112
	add	__a3, __v4, __ip
	ldmia	__a3, {__a1-__a2}
	add	__ip, __v5, __ip
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	adr	__a3, |L..50|+24
	ldmia	__a3, {__a3-__a4}
	bl	|__gtdf2|
	cmp	__a1, #0
	ble	|L..24|
	ldr	__ip, [__sp, #0]
	add	__ip, __ip, #1
	str	__ip, [__sp, #0]
	mov	__ip, #255
	strb	__ip, [__v6, #0]
	mov	__a3, #127
	strb	__a3, [__v6, #1]
	b	|L..25|
|L..24|
	adr	__a3, |L..50|
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__ltdf2|
	cmp	__a1, #0
	bge	|L..26|
	ldmia	__sp, {__a3, __ip}	; phole ldm
	add	__a3, __a3, #1
	str	__a3, [__sp, #0]
	strb	__ip, [__v6, #0]
	mov	__ip, #128
	strb	__ip, [__v6, #1]
	b	|L..25|
|L..26|
	adr	__a3, |L..50|+8
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__gtdf2|
	cmp	__a1, #0
	ble	|L..28|
	adr	__a3, |L..50|+16
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	b	|L..43|
|L..51|
	ALIGN
|L..50|
	DCD &c0e00000, &0	; double -3.27680000000000000000e4
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD &3fe00000, &0	; double 5.00000000000000000000e-1
	DCD &40dfffc0, &0	; double 3.27670000000000000000e4
|L..28|
	adr	__a3, |L..52|
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
|L..43|
	bl	|__fixdfsi|
	strb	__a1, [__v6, #0]
	mov	__a1, __a1, asr #8
	strb	__a1, [__v6, #1]
|L..25|
	sub	__v5, __v5, #128
	sub	__v4, __v4, #256
	add	__v6, __v6, #4
	ldr	__a3, [__sp, #8]
	mov	__ip, #15
	str	__ip, [__sp, #4]
	add	__v4, __v4, __a3
|L..33|
	ldmdb	__v4, {__a1-__a2}
	mov	__v1, __v5
	bl	|__negdf2|
	ldmia	__v1!, {__a3-__a4}
	bl	|__muldf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #16
	ldmia	__ip, {__a1-__a2}
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #24
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, #16
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #32
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, #24
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #40
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, #32
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #48
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, #40
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #56
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, #48
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #64
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, #56
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #72
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, #64
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #80
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, #72
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #88
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, #80
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #96
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, #88
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #104
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, #96
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #112
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, #104
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	sub	__ip, __v4, #120
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v5, #112
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	ldmia	__v4, {__a1-__a2}
	add	__ip, __v5, #120
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	adr	__a3, |L..52|+8
	ldmia	__a3, {__a3-__a4}
	bl	|__gtdf2|
	cmp	__a1, #0
	ble	|L..34|
	ldr	__a3, [__sp, #0]
	add	__a3, __a3, #1
	str	__a3, [__sp, #0]
	mov	__ip, #255
	strb	__ip, [__v6, #0]
	mov	__a3, #127
	strb	__a3, [__v6, #1]
	b	|L..32|
|L..53|
	ALIGN
|L..52|
	DCD &3fe00000, &0	; double 5.00000000000000000000e-1
	DCD &40dfffc0, &0	; double 3.27670000000000000000e4
|L..34|
	adr	__a3, |L..54|
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__ltdf2|
	cmp	__a1, #0
	bge	|L..36|
	ldr	__ip, [__sp, #0]
	add	__ip, __ip, #1
	str	__ip, [__sp, #0]
	mov	__ip, #0
	strb	__ip, [__v6, #0]
	mov	__a3, #128
	strb	__a3, [__v6, #1]
	b	|L..32|
|L..36|
	adr	__a3, |L..54|+8
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__gtdf2|
	cmp	__a1, #0
	ble	|L..38|
	adr	__a3, |L..54|+16
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__adddf3|
	b	|L..44|
|L..38|
	adr	__a3, |L..54|+16
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__subdf3|
|L..44|
	bl	|__fixdfsi|
	strb	__a1, [__v6, #0]
	mov	__a1, __a1, asr #8
	strb	__a1, [__v6, #1]
|L..32|
	sub	__v5, __v5, #128
	sub	__v4, __v4, #256
	ldr	__a3, [__sp, #4]
	add	__v6, __v6, #4
	subs	__a3, __a3, #1
	str	__a3, [__sp, #4]
	bne	|L..33|
	ldr	__a3, [__fp, #4]
	ldr	__ip, [__a3, #0]
	ldr	__a1, [__sp, #0]
	add	__ip, __ip, #128
	str	__ip, [__a3, #0]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..55|
	ALIGN
|L..54|
	DCD &c0e00000, &0	; double -3.27680000000000000000e4
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD &3fe00000, &0	; double 5.00000000000000000000e-1
	ALIGN
	EXPORT	|synth_1to1_mono|
|synth_1to1_mono|
	; args = 0, pretend = 0, frame = 136, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #136
	mov	__v2, __a3
	add	__v3, __sp, #4
	mov	__v1, #0
	add	__ip, __sp, #132
	mov	__v4, __a4
	mov	__a3, __v1
	str	__v1, [__sp, #132]
	mov	__a4, __v3
	str	__ip, [__sp, #0]
	bl	|synth_1to1|
	ldr	__ip, [__v4, #0]
	add	__v2, __v2, __ip
|L..6|
	ldr	__ip, [__v3], #4	; loadhi
	add	__v1, __v1, #1
	cmp	__v1, #31
	strb	__ip, [__v2, #0]
	mov	__ip, __ip, asr #8
	strb	__ip, [__v2, #1]
	add	__v2, __v2, #2
	ble	|L..6|
	ldr	__ip, [__v4, #0]
	add	__ip, __ip, #64
	str	__ip, [__v4, #0]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __fp, __sp, __pc}
	END
