; Generated by gcc 2.95.2 19991024 (release) for ARM/RISC OS

 get fpmacros.s

__r0	RN	0
__a1	RN	0
__a2	RN	1
__a3	RN	2
__a4	RN	3
__v1	RN	4
__v2	RN	5
__v3	RN	6
__v4	RN	7
__v5	RN	8
__v6	RN	9
__sl	RN	10
__fp	RN	11
__ip	RN	12
__sp	RN	13
__lr	RN	14
__pc	RN	15
__f0	FN	0
__f1	FN	1
__f2	FN	2
__f3	FN	3
__f4	FN	4
__f5	FN	5
__f6	FN	6
__f7	FN	7
	AREA |C$$code1|, CODE, READONLY
|gcc2_compiled.|
	EXPORT	|slen1_tab|
|slen1_tab|
	DCB	0
	DCB	0
	DCB	0
	DCB	0
	DCB	3
	DCB	1
	DCB	1
	DCB	1
	DCB	2
	DCB	2
	DCB	2
	DCB	3
	DCB	3
	DCB	3
	DCB	4
	DCB	4
	EXPORT	|slen2_tab|
|slen2_tab|
	DCB	0
	DCB	1
	DCB	2
	DCB	3
	DCB	0
	DCB	1
	DCB	2
	DCB	3
	DCB	1
	DCB	2
	DCB	3
	DCB	1
	DCB	2
	DCB	3
	DCB	2
	DCB	3
	EXPORT	|nr_of_sfb_block|
	ALIGN
|nr_of_sfb_block|
	DCD	6
	DCD	5
	DCD	5
	DCD	5
	DCD	9
	DCD	9
	DCD	9
	DCD	9
	DCD	6
	DCD	9
	DCD	9
	DCD	9
	DCD	6
	DCD	5
	DCD	7
	DCD	3
	DCD	9
	DCD	9
	DCD	12
	DCD	6
	DCD	6
	DCD	9
	DCD	12
	DCD	6
	DCD	11
	DCD	10
	DCD	0
	DCD	0
	DCD	18
	DCD	18
	DCD	0
	DCD	0
	DCD	15
	DCD	18
	DCD	0
	DCD	0
	DCD	7
	DCD	7
	DCD	7
	DCD	0
	DCD	12
	DCD	12
	DCD	12
	DCD	0
	DCD	6
	DCD	15
	DCD	12
	DCD	0
	DCD	6
	DCD	6
	DCD	6
	DCD	3
	DCD	12
	DCD	9
	DCD	9
	DCD	6
	DCD	6
	DCD	12
	DCD	9
	DCD	6
	DCD	8
	DCD	8
	DCD	5
	DCD	0
	DCD	15
	DCD	12
	DCD	9
	DCD	0
	DCD	6
	DCD	18
	DCD	9
	DCD	0
	EXPORT	|pretab|
|pretab|
	DCB	0
	DCB	0
	DCB	0
	DCB	0
	DCB	0
	DCB	0
	DCB	0
	DCB	0
	DCB	0
	DCB	0
	DCB	0
	DCB	1
	DCB	1
	DCB	1
	DCB	1
	DCB	2
	DCB	2
	DCB	3
	DCB	3
	DCB	3
	DCB	2
	DCB	0
	EXPORT	|sfBandIndex|
	ALIGN
|sfBandIndex|
	DCD	0
	DCD	6
	DCD	12
	DCD	18
	DCD	24
	DCD	30
	DCD	36
	DCD	44
	DCD	54
	DCD	66
	DCD	80
	DCD	96
	DCD	116
	DCD	140
	DCD	168
	DCD	200
	DCD	238
	DCD	284
	DCD	336
	DCD	396
	DCD	464
	DCD	522
	DCD	576
	DCD	0
	DCD	4
	DCD	8
	DCD	12
	DCD	18
	DCD	24
	DCD	32
	DCD	42
	DCD	56
	DCD	74
	DCD	100
	DCD	132
	DCD	174
	DCD	192
	DCD	0
	DCD	6
	DCD	12
	DCD	18
	DCD	24
	DCD	30
	DCD	36
	DCD	44
	DCD	54
	DCD	66
	DCD	80
	DCD	96
	DCD	114
	DCD	136
	DCD	162
	DCD	194
	DCD	232
	DCD	278
	DCD	332
	DCD	394
	DCD	464
	DCD	540
	DCD	576
	DCD	0
	DCD	4
	DCD	8
	DCD	12
	DCD	18
	DCD	26
	DCD	36
	DCD	48
	DCD	62
	DCD	80
	DCD	104
	DCD	136
	DCD	180
	DCD	192
	DCD	0
	DCD	6
	DCD	12
	DCD	18
	DCD	24
	DCD	30
	DCD	36
	DCD	44
	DCD	54
	DCD	66
	DCD	80
	DCD	96
	DCD	116
	DCD	140
	DCD	168
	DCD	200
	DCD	238
	DCD	284
	DCD	336
	DCD	396
	DCD	464
	DCD	522
	DCD	576
	DCD	0
	DCD	4
	DCD	8
	DCD	12
	DCD	18
	DCD	26
	DCD	36
	DCD	48
	DCD	62
	DCD	80
	DCD	104
	DCD	134
	DCD	174
	DCD	192
	DCD	0
	DCD	4
	DCD	8
	DCD	12
	DCD	16
	DCD	20
	DCD	24
	DCD	30
	DCD	36
	DCD	44
	DCD	52
	DCD	62
	DCD	74
	DCD	90
	DCD	110
	DCD	134
	DCD	162
	DCD	196
	DCD	238
	DCD	288
	DCD	342
	DCD	418
	DCD	576
	DCD	0
	DCD	4
	DCD	8
	DCD	12
	DCD	16
	DCD	22
	DCD	30
	DCD	40
	DCD	52
	DCD	66
	DCD	84
	DCD	106
	DCD	136
	DCD	192
	DCD	0
	DCD	4
	DCD	8
	DCD	12
	DCD	16
	DCD	20
	DCD	24
	DCD	30
	DCD	36
	DCD	42
	DCD	50
	DCD	60
	DCD	72
	DCD	88
	DCD	106
	DCD	128
	DCD	156
	DCD	190
	DCD	230
	DCD	276
	DCD	330
	DCD	384
	DCD	576
	DCD	0
	DCD	4
	DCD	8
	DCD	12
	DCD	16
	DCD	22
	DCD	28
	DCD	38
	DCD	50
	DCD	64
	DCD	80
	DCD	100
	DCD	126
	DCD	192
	DCD	0
	DCD	4
	DCD	8
	DCD	12
	DCD	16
	DCD	20
	DCD	24
	DCD	30
	DCD	36
	DCD	44
	DCD	54
	DCD	66
	DCD	82
	DCD	102
	DCD	126
	DCD	156
	DCD	194
	DCD	240
	DCD	296
	DCD	364
	DCD	448
	DCD	550
	DCD	576
	DCD	0
	DCD	4
	DCD	8
	DCD	12
	DCD	16
	DCD	22
	DCD	30
	DCD	42
	DCD	58
	DCD	78
	DCD	104
	DCD	138
	DCD	180
	DCD	192
	DCD	0
	DCD	6
	DCD	12
	DCD	18
	DCD	24
	DCD	30
	DCD	36
	DCD	44
	DCD	54
	DCD	66
	DCD	80
	DCD	96
	DCD	116
	DCD	140
	DCD	168
	DCD	200
	DCD	238
	DCD	284
	DCD	336
	DCD	396
	DCD	464
	DCD	522
	DCD	576
	DCD	0
	DCD	4
	DCD	8
	DCD	12
	DCD	18
	DCD	26
	DCD	36
	DCD	48
	DCD	62
	DCD	80
	DCD	104
	DCD	134
	DCD	174
	DCD	192
	DCD	0
	DCD	6
	DCD	12
	DCD	18
	DCD	24
	DCD	30
	DCD	36
	DCD	44
	DCD	54
	DCD	66
	DCD	80
	DCD	96
	DCD	116
	DCD	140
	DCD	168
	DCD	200
	DCD	238
	DCD	284
	DCD	336
	DCD	396
	DCD	464
	DCD	522
	DCD	576
	DCD	0
	DCD	4
	DCD	8
	DCD	12
	DCD	18
	DCD	26
	DCD	36
	DCD	48
	DCD	62
	DCD	80
	DCD	104
	DCD	134
	DCD	174
	DCD	192
	DCD	0
	DCD	12
	DCD	24
	DCD	36
	DCD	48
	DCD	60
	DCD	72
	DCD	88
	DCD	108
	DCD	132
	DCD	160
	DCD	192
	DCD	232
	DCD	280
	DCD	336
	DCD	400
	DCD	476
	DCD	566
	DCD	568
	DCD	570
	DCD	572
	DCD	574
	DCD	576
	DCD	0
	DCD	8
	DCD	16
	DCD	24
	DCD	36
	DCD	52
	DCD	72
	DCD	96
	DCD	124
	DCD	160
	DCD	162
	DCD	164
	DCD	166
	DCD	192
	ALIGN
	EXPORT	|iteration_init|
|iteration_init|
	; args = 0, pretend = 0, frame = 4, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #4
	ldr	__a3, [__a1, #232]
	str	__a3, [__sp, #0]
	ldr	__a3, [__a3, #20]
	cmp	__a3, #0
	bne	|L..3|
	ldr	__a4, [__sp, #0]
	ldr	__ip, |L..24|
	mov	__v1, #1
	str	__v1, [__a4, #20]
	str	__a3, [__a4, __ip]
	ldr	__ip, |L..24|+4
	ldr	__a3, [__a4, __ip]
	ldr	__v6, |L..24|+8
	add	__a2, __a3, #28
	add	__a3, __a3, #204
	bl	|compute_ath|
	ldr	__ip, |L..24|+12
	mov	__v5, __v1
	adr	__a3, |L..24|+16
	ldmia	__a3, {__a3-__a4}
	mov	__v1, __ip
	stmia	__ip, {__a3-__a4}
|L..7|
	mov	__a1, __v5
	bl	|__floatsidf|
	adr	__a3, |L..24|+24
	ldmia	__a3, {__a3-__a4}
	bl	|pow|
	add	__ip, __v1, __v5, asl #3
	ldr	__a3, |L..24|+32
	add	__v5, __v5, #1
	stmia	__ip, {__a1-__a2}
	cmp	__v5, __a3
	ble	|L..7|
	adr	__a3, |L..24|+16
	ldmia	__a3, {__a3-__a4}
	ldr	__v4, |L..24|+12
	mov	__v5, #1
	stmia	__v6, {__a3-__a4}
|L..12|
	sub	__ip, __v5, #1
	add	__ip, __v4, __ip, asl #3
	mov	__v3, __v5, asl #3
	ldmia	__ip, {__a1-__a2}
	add	__ip, __v3, __v4
	ldmia	__ip, {__a3-__a4}
	bl	|__adddf3|
	adr	__a3, |L..24|+36
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	adr	__a3, |L..24|+44
	ldmia	__a3, {__a3-__a4}
	bl	|pow|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__a1, __v5
	bl	|__floatsidf|
	adr	__a3, |L..24|+36
	ldmia	__a3, {__a3-__a4}
	add	__v5, __v5, #1
	bl	|__subdf3|
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__subdf3|
	ldr	__ip, |L..24|+32
	add	__v3, __v3, __v6
	stmia	__v3, {__a1-__a2}
	cmp	__v5, __ip
	ble	|L..12|
	mov	__v5, #0
|L..17|
	mov	__v4, __v5, asl #3
	add	__v3, __v5, #1
	ldr	__a4, |L..24|+12
	mov	__v6, __v3, asl #3
	add	__ip, __v4, __a4
	ldmia	__ip, {__a1-__a2}
	add	__ip, __v6, __a4
	ldmia	__ip, {__a3-__a4}
	bl	|__adddf3|
	adr	__a3, |L..24|+36
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	adr	__a3, |L..24|+44
	ldmia	__a3, {__a3-__a4}
	bl	|pow|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__a1, __v3
	bl	|__floatsidf|
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__subdf3|
	ldr	__a3, |L..24|+52
	mov	__v5, __v3
	ldr	__ip, |L..24|+56
	add	__v4, __v4, __a3
	cmp	__v5, __ip
	stmia	__v4, {__a1-__a2}
	ble	|L..17|
	add	__ip, __v6, __a3
	adr	__a3, |L..24|+36
	ldmia	__a3, {__a3-__a4}
	mov	__v5, #0
	stmia	__ip, {__a3-__a4}
|L..22|
	sub	__v2, __v5, #210
	mov	__a1, __v2
	bl	|__floatsidf|
	adr	__a3, |L..24|+60
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..24|+68
	ldmia	__a1, {__a1-__a2}
	bl	|pow|
	ldr	__a4, |L..24|+76
	mov	__v1, __v5, asl #3
	add	__ip, __v1, __a4
	stmia	__ip, {__a1-__a2}
	mov	__a1, __v2
	bl	|__floatsidf|
	adr	__a3, |L..24|+80
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..24|+68
	ldmia	__a1, {__a1-__a2}
	bl	|pow|
	ldr	__a3, |L..24|+88
	add	__v5, __v5, #1
	ldr	__ip, |L..24|+92
	add	__v1, __v1, __a3
	cmp	__v5, __ip
	stmia	__v1, {__a1-__a2}
	ble	|L..22|
	ldr	__a1, [__sp, #0]
	bl	|huffman_init|
|L..3|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..25|
	ALIGN
|L..24|
	DCD	32088
	DCD	228128
	DCD	|adj43asm|
	DCD	|pow43|
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD &3ff55555, &55555555	; double 1.33333333333333325932e0
	DCD	8207
	DCD &3fe00000, &0	; double 5.00000000000000000000e-1
	DCD &3fe80000, &0	; double 7.50000000000000000000e-1
	DCD	|adj43|
	DCD	8206
	DCD &bfc80000, &0	; double -1.87500000000000000000e-1
	DCD &40000000, &0	; double 2.00000000000000000000e0
	DCD	|ipow20|
	DCD &3fd00000, &0	; double 2.50000000000000000000e-1
	DCD	|pow20|
	DCD	329
	ALIGN
	EXPORT	|compute_ath|
|compute_ath|
	; args = 0, pretend = 0, frame = 28, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #28
	mov	__v6, __a1
	ldr	__ip, [__v6, #232]
	str	__ip, [__sp, #8]
	ldr	__a1, [__v6, #12]
	str	__a2, [__sp, #0]
	mov	__v5, #0
	str	__a3, [__sp, #4]
	bl	|__floatsidf|
	add	__a3, __sp, #16
	stmia	__a3, {__a1-__a2}
|L..33|
	ldr	__ip, [__sp, #8]
	ldr	__a2, [__sp, #0]
	add	__a3, __ip, #66560
	add	__a3, __a3, #536
	ldr	__a1, [__a3, __v5, asl #2]
	add	__ip, __v5, #1
	ldr	__ip, [__a3, __ip, asl #2]
	mov	__a4, __v5, asl #3
	str	__ip, [__sp, #12]
	add	__ip, __a4, __a2
	adr	__a2, |L..71|
	ldmia	__a2, {__a2-__a3}
	stmia	__ip, {__a2-__a3}
	ldr	__a3, [__sp, #12]
	mov	__v4, __a1
	str	__a4, [__sp, #24]
	cmp	__v4, __a3
	bge	|L..32|
|L..37|
	mov	__a1, __v4
	bl	|__floatsidf|
	add	__ip, __sp, #16
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	adr	__a3, |L..71|+8
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a3, __v6
	ldr	__v1, [__v6, #232]
	bl	|ATHformula|
	ldr	__ip, |L..71|+16
	ldr	__a3, [__v1, __ip]
	mov	__v2, __a2
	mov	__v1, __a1
	cmp	__a3, #0
	adr	__a3, |L..71|+20
	ldmia	__a3, {__a3-__a4}
	bne	|L..69|
	adr	__a3, |L..71|+28
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
|L..69|
	bl	|__subdf3|
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__a1, [__v6, #172]	; float
	bl	|__extendsfdf2|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	adr	__a3, |L..71|+36
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..71|+44
	ldmia	__a1, {__a1-__a2}
	bl	|pow|
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__a2, [__sp, #24]
	ldr	__a3, [__sp, #0]
	add	__v3, __a2, __a3
	ldmia	__v3, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__ledf2|
	cmp	__a1, #0
	ldmgtia	__v3, {__v1-__v2}
|L..41|
	ldr	__ip, [__sp, #12]
	add	__v4, __v4, #1
	stmia	__v3, {__v1-__v2}
	cmp	__v4, __ip
	blt	|L..37|
|L..32|
	add	__v5, __v5, #1
	cmp	__v5, #21
	ble	|L..33|
	mov	__v5, #0
|L..47|
	ldr	__a2, [__sp, #8]
	ldr	__a3, [__sp, #4]
	add	__ip, __a2, #66560
	add	__ip, __ip, #628
	ldr	__a1, [__ip, __v5, asl #2]
	add	__a4, __v5, #1
	ldr	__ip, [__ip, __a4, asl #2]
	mov	__lr, __v5, asl #3
	str	__ip, [__sp, #12]
	add	__ip, __lr, __a3
	adr	__a2, |L..71|
	ldmia	__a2, {__a2-__a3}
	stmia	__ip, {__a2-__a3}
	mov	__v5, __a4
	ldr	__a3, [__sp, #12]
	mov	__v4, __a1
	str	__lr, [__sp, #24]
	cmp	__v4, __a3
	bge	|L..46|
|L..51|
	mov	__a1, __v4
	bl	|__floatsidf|
	add	__ip, __sp, #16
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	adr	__a3, |L..71|+52
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a3, __v6
	ldr	__v1, [__v6, #232]
	bl	|ATHformula|
	ldr	__ip, |L..71|+16
	ldr	__a3, [__v1, __ip]
	mov	__v2, __a2
	mov	__v1, __a1
	cmp	__a3, #0
	adr	__a3, |L..71|+20
	ldmia	__a3, {__a3-__a4}
	bne	|L..70|
	adr	__a3, |L..71|+28
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
|L..70|
	bl	|__subdf3|
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__a1, [__v6, #172]	; float
	bl	|__extendsfdf2|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	adr	__a3, |L..71|+36
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..71|+44
	ldmia	__a1, {__a1-__a2}
	bl	|pow|
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__a2, [__sp, #24]
	ldr	__a3, [__sp, #4]
	add	__v3, __a2, __a3
	ldmia	__v3, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__ledf2|
	cmp	__a1, #0
	ldmgtia	__v3, {__v1-__v2}
|L..55|
	ldr	__ip, [__sp, #12]
	add	__v4, __v4, #1
	stmia	__v3, {__v1-__v2}
	cmp	__v4, __ip
	blt	|L..51|
|L..46|
	cmp	__v5, #12
	ble	|L..47|
	ldr	__ip, [__v6, #164]
	cmp	__ip, #0
	beq	|L..58|
	mov	__v5, #0
	adr	__a3, |L..71|+60
	ldmia	__a3, {__a3-__a4}
|L..62|
	ldr	__a2, [__sp, #0]
	add	__ip, __a2, __v5, asl #3
	add	__v5, __v5, #1
	cmp	__v5, #21
	stmia	__ip, {__a3-__a4}
	ble	|L..62|
	mov	__v5, #0
	adr	__a3, |L..71|+60
	ldmia	__a3, {__a3-__a4}
|L..67|
	ldr	__a2, [__sp, #4]
	add	__ip, __a2, __v5, asl #3
	add	__v5, __v5, #1
	cmp	__v5, #12
	stmia	__ip, {__a3-__a4}
	ble	|L..67|
|L..58|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..72|
	ALIGN
|L..71|
	DCD &547d42ae, &a2879f2e	; double 9.99999999999999967336e98
	DCD &3f4c71c7, &1c71c71c	; double 8.68055555555555507369e-4
	DCD	227012
	DCD &40590000, &0	; double 1.00000000000000000000e2
	DCD &405c8000, &0	; double 1.14000000000000000000e2
	DCD &3fb99999, &9999999a	; double 1.00000000000000005551e-1
	DCD &40240000, &0	; double 1.00000000000000000000e1
	DCD &3f655555, &55555555	; double 2.60416666666666652211e-3
	DCD &3841039d, &428a8b8f	; double 1.00000000000000006632e-37
	ALIGN
	EXPORT	|on_pe|
|on_pe|
	; args = 8, pretend = 0, frame = 44, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #44
	str	__a3, [__sp, #20]
	mov	__ip, __a1
	str	__a4, [__sp, #24]
	str	__a2, [__sp, #16]
	mov	__a3, __sp
	ldr	__a2, [__fp, #4]
	add	__a4, __sp, #4
	ldr	__ip, [__ip, #232]
	mov	__v6, #0
	str	__ip, [__sp, #28]
	bl	|ResvMaxBits|
	ldr	__a1, [__sp, #28]
	ldmia	__sp, {__a3, __a4}
	add	__a3, __a3, __a4
	ldr	__a2, [__a1, #44]
	str	__v6, [__sp, #32]
	str	__a3, [__sp, #36]
	cmp	__v6, __a2
	bge	|L..81|
	add	__ip, __sp, #8
	str	__ip, [__sp, #40]
|L..83|
	ldr	__a1, [__sp, #0]
	ldr	__lr, [__fp, #8]
	mov	__v1, __v6, asl #3
	ldr	__a3, [__sp, #20]
	rsb	__ip, __lr, __lr, asl #3
	mov	__ip, __ip, asl #5
	add	__ip, __ip, #48
	add	__ip, __a3, __ip
	rsb	__a3, __v6, __v1
	add	__v3, __ip, __a3, asl #4
	bl	|__divsi3|
	ldr	__ip, |L..103|
	ldr	__a4, [__sp, #24]
	cmp	__a1, __ip
	movge	__a1, __ip
	str	__a1, [__a4, __v6, asl #2]
	ldr	__ip, |L..103|+4
	ldr	__lr, [__sp, #28]
	ldr	__a3, [__lr, __ip]
	cmp	__a3, #0
	beq	|L..84|
	bl	|__floatsidf|
	ldr	__a3, [__sp, #16]
	ldr	__a4, [__fp, #8]
	add	__ip, __a3, __a4, asl #4
	add	__ip, __v1, __ip
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	adr	__a3, |L..103|+8
	ldmia	__a3, {__a3-__a4}
	mov	__v3, __v6, asl #2
	bl	|__muldf3|
	ldr	__ip, [__sp, #24]
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__a1, [__ip, __v6, asl #2]
	add	__v4, __sp, #8
	bl	|__floatsidf|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	bl	|__fixdfsi|
	ldr	__lr, [__sp, #40]
	mov	__v5, __v3
	str	__a1, [__v3, __lr]
	b	|L..85|
|L..84|
	ldr	__a1, [__sp, #16]
	ldr	__a2, [__fp, #8]
	mov	__v2, __v6, asl #2
	adr	__a3, |L..103|+16
	ldmia	__a3, {__a3-__a4}
	add	__ip, __a1, __a2, asl #4
	add	__ip, __v1, __ip
	ldmia	__ip, {__a1-__a2}
	add	__v1, __sp, #8
	bl	|__subdf3|
	adr	__a3, |L..103|+24
	ldmia	__a3, {__a3-__a4}
	mov	__v5, __v2
	bl	|__muldf3|
	bl	|__fixdfsi|
	ldr	__ip, [__v3, #24]
	mov	__v4, __v1
	str	__a1, [__v2, __v1]
	cmp	__ip, #2
	bne	|L..86|
	ldr	__ip, [__fp, #4]
	mov	__a3, __ip
	cmp	__a3, #0
	addlt	__ip, __a3, #3
	mov	__ip, __ip, asr #2
	cmp	__a1, __ip
	strlt	__ip, [__v5, __v4]
|L..86|
	ldr	__a1, [__v5, __v4]
	bl	|__floatsidf|
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__a1, [__fp, #4]
	bl	|__floatsidf|
	adr	__a3, |L..103|+32
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__gtdf2|
	cmp	__a1, #0
	ble	|L..88|
	ldr	__a1, [__fp, #4]
	bl	|__floatsidf|
	adr	__a3, |L..103|+32
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|__fixdfsi|
	str	__a1, [__v5, __v4]
|L..88|
	ldr	__ip, [__v5, __v4]
	cmp	__ip, #0
	movlt	__ip, #0
	strlt	__ip, [__v5, __v4]
|L..89|
	ldr	__a4, [__sp, #24]
	ldr	__ip, [__v5, __v4]
	ldr	__a3, [__a4, __v6, asl #2]
	add	__ip, __a3, __ip
	cmp	__ip, #4096
	blt	|L..85|
	rsb	__ip, __a3, #4080
	add	__ip, __ip, #15
	cmp	__ip, #0
	movlt	__ip, #0
	str	__ip, [__v5, __v4]
|L..85|
	ldr	__ip, [__v5, __v4]
	ldr	__lr, [__sp, #28]
	ldr	__a1, [__sp, #32]
	add	__v6, __v6, #1
	ldr	__a2, [__lr, #44]
	add	__a1, __a1, __ip
	str	__a1, [__sp, #32]
	cmp	__v6, __a2
	blt	|L..83|
|L..81|
	ldr	__ip, [__sp, #4]
	ldr	__a2, [__sp, #32]
	cmp	__a2, __ip
	ble	|L..92|
	ldr	__a3, [__sp, #28]
	ldr	__ip, [__a3, #44]
	mov	__v6, #0
	cmp	__v6, __ip
	bge	|L..92|
	add	__v2, __sp, #8
|L..96|
	ldr	__a3, [__sp, #4]
	mov	__v1, __v6, asl #2
	ldr	__ip, [__v1, __v2]
	ldr	__a2, [__sp, #32]
	mul	__a1, __ip, __a3
	bl	|__divsi3|
	str	__a1, [__v1, __v2]
	ldr	__a4, [__sp, #28]
	ldr	__ip, [__a4, #44]
	add	__v6, __v6, #1
	cmp	__v6, __ip
	blt	|L..96|
|L..92|
	ldr	__lr, [__sp, #28]
	ldr	__ip, [__lr, #44]
	mov	__v6, #0
	cmp	__v6, __ip
	bge	|L..99|
	add	__a2, __sp, #8
|L..101|
	ldr	__a1, [__sp, #24]
	ldr	__a4, [__a2, __v6, asl #2]
	ldr	__ip, [__a1, __v6, asl #2]
	ldr	__a3, [__sp, #4]
	add	__ip, __ip, __a4
	str	__ip, [__a1, __v6, asl #2]
	rsb	__a3, __a4, __a3
	str	__a3, [__sp, #4]
	ldr	__a3, [__sp, #28]
	ldr	__ip, [__a3, #44]
	add	__v6, __v6, #1
	cmp	__v6, __ip
	blt	|L..101|
|L..99|
	ldr	__a1, [__sp, #36]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..104|
	ALIGN
|L..103|
	DCD	4095
	DCD	227012
	DCD &3f5767dc, &e434a9b1	; double 1.42857142857142857019e-3
	DCD &40877000, &0	; double 7.50000000000000000000e2
	DCD &3fe6db6d, &b6db6db7	; double 7.14285714285714301575e-1
	DCD &3fe80000, &0	; double 7.50000000000000000000e-1
	ALIGN
	EXPORT	|reduce_side|
|reduce_side|
	; args = 4, pretend = 0, frame = 0, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	mov	__v3, __a1
	mov	__v2, __a3
	mov	__v1, __a2
	mov	__v5, __a4
	adr	__a1, |L..115|
	ldmia	__a1, {__a1-__a2}
	mov	__a4, __v2
	mov	__a3, __v1
	ldr	__v4, [__fp, #4]
	bl	|__subdf3|
	adr	__a3, |L..115|+8
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	bl	|__adddf3|
	bl	|__truncdfsf2|
	mov	__v1, __a1
	ldr	__a2, |L..115|+16	; float
	bl	|__ltsf2|
	ldr	__ip, |L..115|+16	; float
	cmp	__a1, #0
	movlt	__v1, __ip
	mov	__a1, __v1
	bl	|__extendsfdf2|
	adr	__a3, |L..115|
	ldmia	__a3, {__a3-__a4}
	bl	|__gtdf2|
	cmp	__a1, #0
	ldr	__ip, |L..115|+20	; float
	mov	__a1, __v1
	movgt	__a1, __ip
	bl	|__extendsfdf2|
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__v3, {__a1, __ip}
	add	__a1, __a1, __ip
	bl	|__floatsidf|
	adr	__a3, |L..115|
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	bl	|__fixdfsi|
	ldr	__a4, [__v3, #0]
	ldr	__a3, [__v3, #4]
	rsb	__ip, __a4, #4080
	add	__ip, __ip, #15
	cmp	__a1, __ip
	movlt	__v1, __a1
	movge	__v1, __ip
	cmp	__v1, #0
	movlt	__v1, #0
	cmp	__a3, #124
	ble	|L..110|
	rsb	__ip, __v1, __a3
	cmp	__ip, #125
	ble	|L..111|
	cmp	__a4, __v5
	addlt	__ip, __a4, __v1
	strlt	__ip, [__v3, #0]
|L..112|
	ldr	__ip, [__v3, #4]
	rsb	__ip, __v1, __ip
	str	__ip, [__v3, #4]
	b	|L..110|
|L..111|
	sub	__ip, __a4, #125
	add	__ip, __ip, __a3
	str	__ip, [__v3, #0]
	mov	__a3, #125
	str	__a3, [__v3, #4]
|L..110|
	ldmia	__v3, {__v1, __ip}
	add	__v1, __v1, __ip
	ldr	__a1, [__v3, #0]
	cmp	__v1, __v4
	ble	|L..114|
	mul	__a1, __v4, __a1
	mov	__a2, __v1
	bl	|__divsi3|
	ldr	__ip, [__v3, #4]
	mov	__a2, __v1
	str	__a1, [__v3, #0]
	mul	__a1, __ip, __v4
	bl	|__divsi3|
	str	__a1, [__v3, #4]
|L..114|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __fp, __sp, __pc}
|L..116|
	ALIGN
|L..115|
	DCD &3fe00000, &0	; double 5.00000000000000000000e-1
	DCD &3fd51eb8, &51eb851f	; double 3.30000000000000015543e-1
	DCD &0	; double 0.00000000000000000000e0
	DCD &3f000000	; double 5.00000000000000000000e-1
	ALIGN
	EXPORT	|calc_xmin|
|calc_xmin|
	; args = 4, pretend = 0, frame = 76, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #76
	ldr	__ip, [__a4, #24]
	mov	__a4, #0
	str	__a4, [__sp, #36]
	stmia	__sp, {__a1, __a2, __a3}	; phole stm
	cmp	__ip, #2
	ldr	__ip, [__a1, #232]
	str	__ip, [__sp, #12]
	bne	|L..118|
	str	__a4, [__sp, #20]
	str	__a4, [__sp, #16]
	ldr	__lr, [__a1, #156]
	str	__lr, [__sp, #60]
|L..122|
	ldr	__a1, [__sp, #12]
	ldr	__a2, [__sp, #16]
	add	__ip, __a1, #66560
	add	__a4, __a2, #1
	str	__a4, [__sp, #64]
	add	__ip, __ip, #628
	ldr	__a3, [__ip, __a2, asl #2]
	str	__a3, [__sp, #24]
	add	__a3, __a2, __a2, asl #1
	ldr	__a4, [__ip, __a4, asl #2]
	mov	__a3, __a3, asl #3
	str	__a3, [__sp, #48]
	mov	__v4, #0
	ldr	__ip, [__sp, #24]
	mov	__v3, __a2, asl #3
	str	__a4, [__sp, #28]
	rsb	__a4, __ip, __a4
	str	__a4, [__sp, #32]
|L..126|
	ldr	__v1, [__sp, #24]
	ldr	__lr, [__sp, #28]
	ldr	__a1, [__sp, #36]
	add	__a4, __sp, #48
	adr	__a2, |L..199|
	ldmia	__a2, {__a2-__a3}
	add	__a1, __a1, #1
	str	__a1, [__sp, #68]
	mov	__ip, __v4, asl #3
	stmdb	__a4, {__a2-__a3}
	add	__v4, __v4, #1
	cmp	__v1, __lr
	str	__ip, [__sp, #72]
	bge	|L..128|
|L..130|
	ldr	__lr, [__sp, #4]
	ldr	__a1, [__sp, #20]
	add	__ip, __lr, __a1, asl #3
	add	__a1, __a1, #1
	str	__a1, [__sp, #20]
	ldmia	__ip, {__a3-__a4}
	mov	__a2, __a4
	mov	__a1, __a3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __sp, #48
	ldmdb	__ip, {__a1-__a2}
	bl	|__adddf3|
	add	__lr, __sp, #48
	stmdb	__lr, {__a1-__a2}
	ldr	__a1, [__sp, #28]
	add	__v1, __v1, #1
	cmp	__v1, __a1
	blt	|L..130|
|L..128|
	ldr	__a1, [__sp, #32]
	bl	|__floatsidf|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __sp, #48
	ldmdb	__ip, {__a1-__a2}
	bl	|__divdf3|
	add	__lr, __sp, #48
	stmdb	__lr, {__a1-__a2}
	ldr	__a1, [__sp, #60]
	cmp	__a1, #0
	bne	|L..133|
	ldr	__a2, [__sp, #0]
	ldr	__ip, [__a2, #160]
	cmp	__ip, #0
	beq	|L..132|
|L..133|
	ldr	__a3, |L..199|+8
	ldr	__a4, [__sp, #12]
	ldr	__ip, [__a4, __a3]
	ldmib	__ip, {__a1-__a2}
	add	__ip, __ip, __v3
	add	__ip, __ip, #204
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v6, __a2
	mov	__v5, __a1
	b	|L..134|
|L..132|
	ldr	__ip, [__sp, #72]
	ldr	__lr, [__sp, #48]
	ldr	__a1, [__sp, #8]
	add	__v1, __ip, __lr
	add	__ip, __a1, #664
	add	__ip, __ip, __v1
	ldmia	__ip, {__v5-__v6}
	adr	__a3, |L..199|
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__gtdf2|
	cmp	__a1, #0
	ble	|L..135|
	ldr	__a2, [__sp, #8]
	add	__ip, __a2, #176
	add	__ip, __ip, __v1
	ldmia	__ip, {__a3-__a4}
	add	__ip, __sp, #48
	ldmdb	__ip, {__a1-__a2}
	bl	|__muldf3|
	ldr	__lr, [__sp, #12]
	add	__ip, __lr, #32512
	add	__ip, __ip, #148
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__divdf3|
	mov	__v6, __a2
	mov	__v5, __a1
|L..135|
	ldr	__a3, |L..199|+8
	ldr	__a1, [__sp, #12]
	ldr	__ip, [__a1, __a3]
	ldmib	__ip, {__a1-__a2}
	add	__ip, __ip, __v3
	add	__ip, __ip, #204
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__a2, __v6
	mov	__a1, __v5
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__gedf2|
	cmp	__a1, #0
	movlt	__v6, __v2
	movlt	__v5, __v1
|L..134|
	ldr	__a1, [__sp, #32]
	ldr	__a2, [__sp, #72]
	ldr	__a4, [__sp, #48]
	ldr	__lr, [__fp, #4]
	add	__a3, __a2, __a4
	add	__ip, __lr, #176
	add	__v1, __ip, __a3
	bl	|__floatsidf|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__muldf3|
	stmia	__v1, {__a1-__a2}
	ldr	__ip, |L..199|+12
	ldr	__a1, [__sp, #12]
	ldr	__a3, [__a1, __ip]
	cmp	__a3, #0
	beq	|L..137|
	ldr	__a2, [__sp, #16]
	cmp	__a2, #5
	bgt	|L..138|
	ldr	__ip, |L..199|+16
	ldr	__a1, [__a1, __ip]	; float
	b	|L..196|
|L..138|
	ldr	__a3, [__sp, #16]
	cmp	__a3, #10
	bgt	|L..140|
	ldr	__ip, |L..199|+20
	ldr	__a4, [__sp, #12]
	ldr	__a1, [__a4, __ip]	; float
	b	|L..196|
|L..200|
	ALIGN
|L..199|
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD	228128
	DCD	227012
	DCD	228088
	DCD	228092
|L..140|
	ldr	__ip, |L..201|
	ldr	__lr, [__sp, #12]
	ldr	__a1, [__lr, __ip]	; float
|L..196|
	bl	|__extendsfdf2|
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__v1, {__a1-__a2}
	bl	|__muldf3|
	stmia	__v1, {__a1-__a2}
|L..137|
	ldr	__a3, |L..201|+4
	ldr	__a1, [__sp, #12]
	ldr	__ip, [__a1, __a3]
	ldmib	__ip, {__a1-__a2}
	add	__ip, __ip, __v3
	add	__ip, __ip, #204
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __sp, #48
	ldmdb	__ip, {__a1-__a2}
	bl	|__gtdf2|
	ldr	__ip, |L..201|+8
	ldr	__lr, [__sp, #12]
	ldr	__a2, [__sp, #36]
	ldr	__a4, [__sp, #68]
	cmp	__a1, #0
	ldr	__a3, [__lr, __ip]
	movgt	__a2, __a4
	str	__a2, [__sp, #36]
	cmp	__a3, #0
	beq	|L..125|
	ldr	__lr, [__sp, #0]
	ldr	__ip, [__lr, #116]
	cmp	__ip, #3
	cmpne	__ip, #0
	bne	|L..125|
	ldr	__ip, [__lr, #40]
	cmp	__ip, #1
	bgt	|L..125|
	ldr	__a1, [__sp, #72]
	ldr	__a2, [__sp, #48]
	ldr	__a3, [__fp, #4]
	add	__ip, __a1, __a2
	add	__v1, __a3, #176
	add	__v1, __v1, __ip
	ldmia	__v1, {__a1-__a2}
	adr	__a3, |L..201|+12
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	stmia	__v1, {__a1-__a2}
|L..125|
	cmp	__v4, #2
	ble	|L..126|
	ldr	__a4, [__sp, #64]
	str	__a4, [__sp, #16]
	cmp	__a4, #12
	ble	|L..122|
	ldr	__lr, [__sp, #0]
	ldr	__ip, [__lr, #184]
	cmp	__ip, #0
	beq	|L..158|
	ldr	__a2, [__fp, #4]
	mov	__a1, #0
	str	__a1, [__sp, #16]
	add	__a2, __a2, #176
	str	__a2, [__sp, #56]
|L..150|
	ldr	__a3, [__sp, #16]
	mov	__v4, #1
	ldr	__a4, [__sp, #16]
	add	__a3, __a3, __v4
	add	__ip, __a4, __a4, asl #1
	str	__a3, [__sp, #64]
	mov	__ip, __ip, asl #3
	str	__ip, [__sp, #52]
|L..154|
	ldr	__lr, [__sp, #12]
	adr	__a1, |L..201|+20
	ldmia	__a1, {__a1-__a2}
	add	__ip, __lr, #32512
	ldr	__lr, [__sp, #52]
	add	__ip, __ip, #140
	ldmia	__ip, {__v1-__v2}
	add	__ip, __lr, __v4, asl #3
	ldr	__lr, [__sp, #56]
	mov	__a4, __v2
	mov	__a3, __v1
	add	__v3, __lr, __ip
	bl	|__subdf3|
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__v3, {__a1-__a2}
	bl	|__muldf3|
	mov	__v6, __a2
	mov	__v5, __a1
	ldr	__a1, [__sp, #52]
	sub	__ip, __v4, #1
	ldr	__a2, [__sp, #56]
	add	__ip, __a1, __ip, asl #3
	add	__ip, __a2, __ip
	ldmia	__ip, {__a1-__a2}
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__adddf3|
	mov	__v6, __a2
	mov	__v5, __a1
	ldmia	__v3, {__a1-__a2}
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__ltdf2|
	cmp	__a1, #0
	stmltia	__v3, {__v5-__v6}
|L..153|
	add	__v4, __v4, #1
	cmp	__v4, #2
	ble	|L..154|
	ldr	__a3, [__sp, #64]
	str	__a3, [__sp, #16]
	cmp	__a3, #12
	ble	|L..150|
	b	|L..158|
|L..118|
	ldr	__ip, |L..201|+8
	ldr	__a4, [__sp, #12]
	ldr	__a3, [__a4, __ip]
	cmp	__a3, #0
	beq	|L..159|
	ldr	__ip, [__sp, #36]
	ldr	__lr, [__sp, #0]
	str	__ip, [__sp, #16]
	ldr	__lr, [__lr, #156]
	str	__lr, [__sp, #60]
|L..163|
	ldr	__a1, [__sp, #12]
	ldr	__a2, [__sp, #16]
	add	__a3, __a1, #66560
	add	__ip, __a2, #1
	str	__ip, [__sp, #64]
	add	__a3, __a3, #536
	ldr	__ip, [__a3, __ip, asl #2]
	str	__ip, [__sp, #28]
	ldr	__v1, [__a3, __a2, asl #2]
	ldr	__a3, [__sp, #36]
	mov	__v3, __a2, asl #3
	adr	__a1, |L..201|+28
	ldmia	__a1, {__a1-__a2}
	add	__a3, __a3, #1
	str	__a3, [__sp, #68]
	add	__a3, __sp, #48
	cmp	__v1, __ip
	stmdb	__a3, {__a1-__a2}
	bge	|L..165|
|L..167|
	ldr	__a4, [__sp, #4]
	add	__ip, __a4, __v1, asl #3
	ldmia	__ip, {__a1-__a2}
	mov	__a4, __a2
	mov	__a3, __a1
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __sp, #48
	ldmdb	__ip, {__a1-__a2}
	bl	|__adddf3|
	add	__lr, __sp, #48
	stmdb	__lr, {__a1-__a2}
	ldr	__a1, [__sp, #28]
	add	__v1, __v1, #1
	cmp	__v1, __a1
	blt	|L..167|
|L..165|
	ldr	__a2, [__sp, #60]
	cmp	__a2, #0
	beq	|L..169|
	ldr	__a3, |L..201|+4
	ldr	__a4, [__sp, #12]
	ldr	__ip, [__a4, __a3]
	ldmib	__ip, {__a1-__a2}
	add	__ip, __ip, __v3
	add	__ip, __ip, #28
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v6, __a2
	mov	__v5, __a1
	b	|L..170|
|L..202|
	ALIGN
|L..201|
	DCD	228096
	DCD	228128
	DCD	227012
	DCD &3f50624d, &d2f1a9fc	; double 1.00000000000000002082e-3
	DCD &3ff00000, &0	; double 1.00000000000000000000e0
	DCD &0, &0	; double 0.00000000000000000000e0
|L..169|
	ldr	__lr, [__sp, #8]
	add	__ip, __lr, #488
	add	__ip, __ip, __v3
	ldmia	__ip, {__v5-__v6}
	adr	__a3, |L..203|
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__gtdf2|
	cmp	__a1, #0
	ble	|L..171|
	ldr	__a1, [__sp, #8]
	add	__ip, __a1, __v3
	ldmia	__ip, {__a3-__a4}
	add	__ip, __sp, #48
	ldmdb	__ip, {__a1-__a2}
	bl	|__muldf3|
	ldr	__lr, [__sp, #12]
	add	__ip, __lr, #32512
	add	__ip, __ip, #148
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__divdf3|
	mov	__v6, __a2
	mov	__v5, __a1
|L..171|
	ldr	__a3, |L..203|+8
	ldr	__a1, [__sp, #12]
	ldr	__ip, [__a1, __a3]
	ldmib	__ip, {__a1-__a2}
	add	__ip, __ip, __v3
	add	__ip, __ip, #28
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__a2, __v6
	mov	__a1, __v5
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__gedf2|
	cmp	__a1, #0
	movlt	__v6, __v2
	movlt	__v5, __v1
|L..170|
	ldr	__a2, [__sp, #16]
	ldr	__a3, [__fp, #4]
	cmp	__a2, #6
	add	__v1, __a3, __v3
	stmia	__v1, {__v5-__v6}
	bgt	|L..173|
	ldr	__ip, |L..203|+12
	ldr	__a4, [__sp, #12]
	ldr	__a1, [__a4, __ip]	; float
	bl	|__extendsfdf2|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v6
	mov	__a1, __v5
	b	|L..197|
|L..173|
	ldr	__ip, [__sp, #16]
	cmp	__ip, #13
	bgt	|L..175|
	ldr	__ip, |L..203|+16
	ldr	__lr, [__sp, #12]
	ldr	__a1, [__lr, __ip]	; float
	b	|L..198|
|L..175|
	ldr	__ip, |L..203|+20
	ldr	__a2, [__sp, #12]
	ldr	__a1, [__a2, __ip]	; float
|L..198|
	bl	|__extendsfdf2|
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__v1, {__a1-__a2}
|L..197|
	bl	|__muldf3|
	stmia	__v1, {__a1-__a2}
	ldr	__a3, |L..203|+8
	ldr	__a4, [__sp, #12]
	ldr	__ip, [__a4, __a3]
	ldmib	__ip, {__a1-__a2}
	add	__ip, __ip, __v3
	add	__ip, __ip, #28
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __sp, #48
	ldmdb	__ip, {__a1-__a2}
	bl	|__gtdf2|
	ldr	__lr, [__sp, #0]
	ldr	__a2, [__sp, #36]
	ldr	__a3, [__sp, #68]
	cmp	__a1, #0
	ldr	__ip, [__lr, #116]
	movgt	__a2, __a3
	str	__a2, [__sp, #36]
	cmp	__ip, #3
	cmpne	__ip, #0
	bne	|L..162|
	ldr	__ip, [__lr, #40]
	cmp	__ip, #1
	bgt	|L..162|
	ldr	__a4, [__fp, #4]
	add	__v1, __a4, __v3
	ldmia	__v1, {__a1-__a2}
	adr	__a3, |L..203|+24
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	stmia	__v1, {__a1-__a2}
|L..162|
	ldr	__ip, [__sp, #64]
	str	__ip, [__sp, #16]
	cmp	__ip, #21
	ble	|L..163|
	b	|L..158|
|L..159|
	ldr	__lr, [__sp, #36]
	ldr	__a1, [__sp, #0]
	str	__lr, [__sp, #16]
	ldr	__a1, [__a1, #156]
	str	__a1, [__sp, #60]
|L..184|
	ldr	__a2, [__sp, #12]
	ldr	__a4, [__sp, #16]
	ldr	__a1, [__sp, #36]
	add	__ip, __a2, #66560
	add	__a3, __a4, #1
	str	__a3, [__sp, #64]
	add	__ip, __ip, #536
	ldr	__lr, [__ip, __a4, asl #2]
	str	__lr, [__sp, #24]
	ldr	__a3, [__ip, __a3, asl #2]
	add	__a1, __a1, #1
	str	__a1, [__sp, #68]
	str	__a3, [__sp, #28]
	mov	__v3, __a4, asl #3
	adr	__a2, |L..203|
	ldmia	__a2, {__a2-__a3}
	add	__a4, __sp, #48
	stmdb	__a4, {__a2-__a3}
	ldr	__ip, [__sp, #28]
	ldr	__v1, [__sp, #24]
	rsb	__ip, __lr, __ip
	ldr	__lr, [__sp, #28]
	str	__ip, [__sp, #32]
	cmp	__v1, __lr
	bge	|L..186|
|L..188|
	ldr	__a1, [__sp, #4]
	add	__ip, __a1, __v1, asl #3
	ldmia	__ip, {__a1-__a2}
	mov	__a4, __a2
	mov	__a3, __a1
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __sp, #48
	ldmdb	__ip, {__a1-__a2}
	bl	|__adddf3|
	add	__lr, __sp, #48
	stmdb	__lr, {__a1-__a2}
	ldr	__a1, [__sp, #28]
	add	__v1, __v1, #1
	cmp	__v1, __a1
	blt	|L..188|
|L..186|
	ldr	__a1, [__sp, #32]
	bl	|__floatsidf|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __sp, #48
	ldmdb	__ip, {__a1-__a2}
	bl	|__divdf3|
	add	__lr, __sp, #48
	stmdb	__lr, {__a1-__a2}
	ldr	__a1, [__sp, #60]
	cmp	__a1, #0
	beq	|L..190|
	ldr	__a3, |L..203|+8
	ldr	__a2, [__sp, #12]
	ldr	__ip, [__a2, __a3]
	ldmib	__ip, {__a1-__a2}
	add	__ip, __ip, __v3
	add	__ip, __ip, #28
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v6, __a2
	mov	__v5, __a1
	b	|L..191|
|L..204|
	ALIGN
|L..203|
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD	228128
	DCD	228088
	DCD	228092
	DCD	228096
	DCD &3f50624d, &d2f1a9fc	; double 1.00000000000000002082e-3
|L..190|
	ldr	__a3, [__sp, #8]
	add	__ip, __a3, #488
	add	__ip, __ip, __v3
	ldmia	__ip, {__v5-__v6}
	adr	__a3, |L..205|
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__gtdf2|
	cmp	__a1, #0
	ble	|L..192|
	ldr	__a4, [__sp, #8]
	add	__ip, __a4, __v3
	ldmia	__ip, {__a3-__a4}
	add	__ip, __sp, #48
	ldmdb	__ip, {__a1-__a2}
	bl	|__muldf3|
	ldr	__lr, [__sp, #12]
	add	__ip, __lr, #32512
	add	__ip, __ip, #148
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__divdf3|
	mov	__v6, __a2
	mov	__v5, __a1
|L..192|
	ldr	__a3, |L..205|+8
	ldr	__a1, [__sp, #12]
	ldr	__ip, [__a1, __a3]
	ldmib	__ip, {__a1-__a2}
	add	__ip, __ip, __v3
	add	__ip, __ip, #28
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__a2, __v6
	mov	__a1, __v5
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__gedf2|
	cmp	__a1, #0
	movlt	__v6, __v2
	movlt	__v5, __v1
|L..191|
	ldr	__a2, [__fp, #4]
	ldr	__a1, [__sp, #32]
	add	__v1, __a2, __v3
	bl	|__floatsidf|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__muldf3|
	stmia	__v1, {__a1-__a2}
	ldr	__a3, |L..205|+8
	ldr	__a4, [__sp, #12]
	ldr	__ip, [__a4, __a3]
	ldmib	__ip, {__a1-__a2}
	add	__ip, __ip, __v3
	add	__ip, __ip, #28
	ldmia	__ip, {__a3-__a4}
	ldr	__ip, [__sp, #64]
	str	__ip, [__sp, #16]
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__lr, __sp, #48
	ldmdb	__lr, {__a1-__a2}
	bl	|__gtdf2|
	ldr	__a2, [__sp, #36]
	ldr	__a3, [__sp, #68]
	cmp	__a1, #0
	ldr	__a4, [__sp, #16]
	movgt	__a2, __a3
	cmp	__a4, #21
	str	__a2, [__sp, #36]
	ble	|L..184|
|L..158|
	ldr	__a1, [__sp, #36]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..206|
	ALIGN
|L..205|
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD	228128
	ALIGN
	EXPORT	|calc_noise|
|calc_noise|
	; args = 16, pretend = 0, frame = 124, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #124
	adr	__v1, |L..251|
	ldmia	__v1, {__v1-__v2}
	add	__ip, __sp, #48
	stmdb	__ip, {__v1-__v2}
	mov	__lr, #0
	str	__lr, [__sp, #28]
	adr	__v1, |L..251|+8
	ldmia	__v1, {__v1-__v2}
	add	__ip, __sp, #64
	stmdb	__ip, {__v1-__v2}
	adr	__v1, |L..251|+16
	ldmia	__v1, {__v1-__v2}
	ldr	__lr, [__sp, #28]
	stmia	__ip, {__v1-__v2}
	str	__a4, [__sp, #12]
	ldr	__ip, [__a4, #24]
	add	__a4, __sp, #48
	ldmdb	__a4, {__a4-__v1}
	add	__v2, __sp, #48
	stmia	__v2, {__a4-__v1}
	stmia	__sp, {__a1, __a2}	; phole stm
	cmp	__ip, #2
	str	__a3, [__sp, #8]
	bne	|L..209|
	ldr	__v1, [__sp, #28]
	ldr	__ip, |L..251|+24
	str	__v1, [__sp, #24]
	ldr	__a3, [__a1, __ip]
	mov	__a1, __v1
	cmp	__a3, #0
	moveq	__a3, #12
	movne	__a3, #13
	cmp	__a1, __a3
	str	__a3, [__sp, #72]
	bge	|L..230|
	ldr	__v2, [__fp, #8]
	ldr	__ip, [__sp, #12]
	add	__v2, __v2, #88
	str	__v2, [__sp, #120]
	add	__ip, __ip, #44
	str	__ip, [__sp, #116]
|L..215|
	add	__a4, __a1, #1
	ldr	__a2, [__sp, #0]
	add	__a3, __a1, __a1, asl #1
	str	__a4, [__sp, #104]
	mov	__v1, __a3, asl #2
	str	__v1, [__sp, #84]
	add	__ip, __a2, #66560
	add	__ip, __ip, #628
	ldr	__a1, [__ip, __a1, asl #2]
	mov	__a3, __a3, asl #3
	str	__a3, [__sp, #88]
	str	__a1, [__sp, #16]
	ldr	__a4, [__ip, __a4, asl #2]
	mov	__a2, #0
	str	__a4, [__sp, #20]
|L..219|
	ldr	__v3, [__sp, #16]
	add	__lr, __lr, #1
	str	__lr, [__sp, #112]
	add	__v2, __a2, #1
	str	__v2, [__sp, #108]
	adr	__v4, |L..251|
	ldmia	__v4, {__v4-__v5}
	ldr	__ip, [__sp, #12]
	ldr	__lr, [__sp, #84]
	ldr	__a1, [__sp, #116]
	ldr	__v1, [__sp, #12]
	ldr	__v2, |L..251|+28
	mov	__v6, __a2, asl #3
	ldr	__a4, [__ip, #68]
	mov	__a3, __a2, asl #2
	ldr	__ip, [__a1, __a3]
	add	__a2, __a3, __lr
	ldr	__a3, [__sp, #120]
	add	__a4, __a4, #1
	ldr	__a1, [__a3, __a2]
	mov	__ip, __ip, asl #3
	ldr	__a3, [__v1, #12]
	add	__ip, __ip, __a1, asl __a4
	rsb	__ip, __ip, __a3
	add	__ip, __v2, __ip, asl #3
	ldmia	__ip, {__a3-__a4}
	add	__v1, __sp, #80
	stmda	__v1, {__a3-__a4}
|L..223|
	ldr	__v2, [__sp, #24]
	ldr	__lr, [__sp, #8]
	ldr	__a2, |L..251|+32
	ldr	__ip, [__lr, __v2, asl #2]
	add	__a1, __sp, #80
	ldmda	__a1, {__a3-__a4}
	add	__ip, __a2, __ip, asl #3
	ldmia	__ip, {__a1-__a2}
	bl	|__muldf3|
	ldr	__a3, [__sp, #4]
	add	__v3, __v3, #1
	ldr	__a4, [__sp, #24]
	mov	__v2, __a2
	mov	__v1, __a1
	add	__ip, __a3, __a4, asl #3
	ldmia	__ip, {__a1-__a2}
	add	__a4, __a4, #1
	str	__a4, [__sp, #24]
	bl	|fabsd|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	mov	__a4, __a2
	mov	__a3, __a1
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v5
	mov	__a1, __v4
	bl	|__adddf3|
	ldr	__v1, [__sp, #20]
	mov	__v5, __a2
	mov	__v4, __a1
	cmp	__v3, __v1
	blt	|L..223|
	ldr	__v2, [__sp, #88]
	mov	__v3, #176
	ldr	__lr, [__fp, #4]
	add	__v1, __v6, __v2
	add	__ip, __lr, __v3
	ldr	__v2, [__fp, #12]
	add	__ip, __ip, __v1
	ldmia	__ip, {__a3-__a4}
	add	__v3, __v2, __v3
	add	__v3, __v3, __v1
	bl	|__divdf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__ip, __sp, #32
	stmia	__ip, {__v1-__v2}
	add	__lr, __sp, #64
	mov	__v5, __v2
	mov	__v4, __v1
	ldmdb	__lr, {__a3-__a4}
	stmia	__v3, {__v1-__v2}
	bl	|__gedf2|
	cmp	__a1, #0
	bge	|L..224|
	add	__a1, __sp, #64
	ldmdb	__a1, {__v4-__v5}
|L..224|
	add	__a2, __sp, #64
	stmdb	__a2, {__v4-__v5}
	add	__a3, __sp, #32
	ldmia	__a3, {__a1-__a2}
	adr	__a3, |L..251|+36
	ldmia	__a3, {__a3-__a4}
	add	__v1, __sp, #32
	ldmia	__v1, {__v3-__v4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__v2, __sp, #32
	ldmia	__v2, {__a1-__a2}
	bl	|__muldf3|
	add	__ip, __sp, #32
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	adr	__a3, |L..251|+44
	ldmia	__a3, {__a3-__a4}
	bl	|__adddf3|
	bl	|log|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__lr, __sp, #64
	ldmia	__lr, {__a1-__a2}
	bl	|__adddf3|
	add	__a3, __sp, #64
	stmia	__a3, {__a1-__a2}
	adr	__a3, |L..251|+8
	ldmia	__a3, {__a3-__a4}
	add	__v1, __sp, #32
	ldmia	__v1, {__a1-__a2}
	bl	|__gedf2|
	cmp	__a1, #0
	adrlt	__v3, |L..251|+8
	ldmltia	__v3, {__v3-__v4}
|L..226|
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|log10|
	adr	__a3, |L..251|+52
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__v2, __sp, #48
	ldmia	__v2, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__ip, __sp, #48
	stmia	__ip, {__a1-__a2}
	adr	__a3, |L..251|+60
	ldmia	__a3, {__a3-__a4}
	add	__lr, __sp, #32
	ldmia	__lr, {__a1-__a2}
	bl	|__gtdf2|
	cmp	__a1, #0
	ble	|L..227|
	ldr	__a1, [__sp, #28]
	add	__a1, __a1, #1
	str	__a1, [__sp, #28]
	add	__a3, __sp, #48
	ldmdb	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__a4, __sp, #48
	stmdb	__a4, {__a1-__a2}
|L..227|
	ldr	__a2, [__sp, #108]
	ldr	__lr, [__sp, #112]
	cmp	__a2, #2
	ble	|L..219|
	ldr	__a1, [__sp, #104]
	b	|L..250|
|L..252|
	ALIGN
|L..251|
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD &3bc79ca1, &c924223	; double 9.99999999999999945153e-21
	DCD &3841039d, &428a8b8f	; double 1.00000000000000006632e-37
	DCD	33244
	DCD	|pow20|
	DCD	|pow43|
	DCD &3fe43958, &10624dd3	; double 6.32000000000000006217e-1
	DCD &3fd78d4f, &df3b645a	; double 3.67999999999999993783e-1
	DCD &40240000, &0	; double 1.00000000000000000000e1
	DCD &3ff00000, &0	; double 1.00000000000000000000e0
|L..250|
	ldr	__v1, [__sp, #72]
	cmp	__a1, __v1
	blt	|L..215|
	b	|L..230|
|L..209|
	ldr	__ip, |L..254|
	ldr	__v2, [__sp, #0]
	ldr	__a3, [__v2, __ip]
	ldr	__a1, [__sp, #28]
	cmp	__a3, #0
	moveq	__a3, #21
	movne	__a3, #22
	cmp	__a1, __a3
	str	__a3, [__sp, #92]
	bge	|L..230|
|L..236|
	ldr	__a2, [__sp, #12]
	ldr	__a3, [__fp, #8]
	ldr	__ip, [__a2, #64]
	mov	__a4, __a1, asl #2
	ldr	__a2, [__a3, __a4]
	cmp	__ip, #0
	beq	|L..237|
	ldr	__ip, |L..254|+4
	ldrb	__a3, [__ip, __a1]	; zero_extendqisi2
	add	__a2, __a2, __a3
|L..237|
	ldr	__v1, [__sp, #0]
	add	__a3, __a1, #1
	adr	__v4, |L..254|+8
	ldmia	__v4, {__v4-__v5}
	add	__ip, __v1, #66560
	add	__ip, __ip, #536
	ldr	__v2, [__ip, __a3, asl #2]
	str	__v2, [__sp, #20]
	ldr	__v3, [__ip, __a4]
	str	__a3, [__sp, #104]
	ldr	__a3, [__sp, #12]
	add	__lr, __lr, #1
	ldr	__ip, [__a3, #68]
	mov	__v6, __a1, asl #3
	str	__lr, [__sp, #112]
	cmp	__v3, __v2
	ldr	__a4, [__a3, #12]
	add	__ip, __ip, #1
	ldr	__a3, |L..254|+16
	sub	__a2, __a4, __a2, asl __ip
	add	__a3, __a3, __a2, asl #3
	ldmia	__a3, {__a4-__v1}
	add	__v2, __sp, #96
	stmia	__v2, {__a4-__v1}
	bge	|L..239|
|L..241|
	ldr	__lr, [__sp, #4]
	add	__ip, __lr, __v3, asl #3
	ldmia	__ip, {__a1-__a2}
	bl	|fabsd|
	add	__v1, __sp, #96
	ldmia	__v1, {__a3-__a4}
	ldr	__v2, [__sp, #8]
	ldr	__lr, |L..254|+20
	ldr	__ip, [__v2, __v3, asl #2]
	mov	__v2, __a2
	mov	__v1, __a1
	add	__ip, __lr, __ip, asl #3
	ldmia	__ip, {__a1-__a2}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	mov	__a4, __a2
	mov	__a3, __a1
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v5
	mov	__a1, __v4
	bl	|__adddf3|
	mov	__v5, __a2
	mov	__v4, __a1
	ldr	__a1, [__sp, #20]
	add	__v3, __v3, #1
	cmp	__v3, __a1
	blt	|L..241|
|L..239|
	ldr	__a3, [__fp, #4]
	mov	__a2, __v5
	mov	__a1, __v4
	ldr	__v2, [__fp, #12]
	add	__ip, __a3, __v6
	ldmia	__ip, {__a3-__a4}
	add	__v1, __v2, __v6
	bl	|__divdf3|
	mov	__v6, __a2
	mov	__v5, __a1
	mov	__v4, __v6
	mov	__v3, __v5
	stmia	__v1, {__v5-__v6}
	add	__ip, __sp, #64
	ldmdb	__ip, {__a3-__a4}
	bl	|__gedf2|
	cmp	__a1, #0
	bge	|L..243|
	add	__lr, __sp, #64
	ldmdb	__lr, {__v3-__v4}
|L..243|
	add	__a1, __sp, #64
	stmdb	__a1, {__v3-__v4}
	adr	__a3, |L..254|+24
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__muldf3|
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__muldf3|
	adr	__a3, |L..254|+32
	ldmia	__a3, {__a3-__a4}
	bl	|__adddf3|
	bl	|log|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__v1, __sp, #64
	ldmia	__v1, {__a1-__a2}
	bl	|__adddf3|
	add	__v2, __sp, #64
	stmia	__v2, {__a1-__a2}
	mov	__v4, __v6
	mov	__v3, __v5
	adr	__a3, |L..254|+40
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__gedf2|
	cmp	__a1, #0
	adrlt	__v3, |L..254|+40
	ldmltia	__v3, {__v3-__v4}
|L..245|
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|log10|
	adr	__a3, |L..254|+48
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__ip, __sp, #48
	ldmia	__ip, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__lr, __sp, #48
	stmia	__lr, {__a1-__a2}
	adr	__a3, |L..254|+56
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__gtdf2|
	cmp	__a1, #0
	ble	|L..246|
	ldr	__a1, [__sp, #28]
	add	__a1, __a1, #1
	str	__a1, [__sp, #28]
	add	__a3, __sp, #48
	ldmdb	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__a4, __sp, #48
	stmdb	__a4, {__a1-__a2}
|L..246|
	ldr	__a1, [__sp, #104]
	ldr	__v1, [__sp, #92]
	ldr	__lr, [__sp, #112]
	cmp	__a1, __v1
	blt	|L..236|
|L..230|
	ldr	__v2, [__fp, #16]
	str	__lr, [__v2, #4]
	ldr	__ip, [__sp, #28]
	str	__ip, [__v2, #0]
	add	__a2, __sp, #48
	ldmia	__a2, {__a1-__a2}
	add	__ip, __v2, #16
	stmia	__ip, {__a1-__a2}
	add	__a3, __sp, #64
	add	__v1, __sp, #48
	adr	__v5, |L..254|+40
	ldmia	__v5, {__v5-__v6}
	ldmdb	__a3, {__v3-__v4}
	add	__ip, __v2, #8
	ldmdb	__v1, {__a4-__v1}
	mov	__a2, __v4
	mov	__a1, __v3
	stmia	__ip, {__a4-__v1}
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__gedf2|
	cmp	__a1, #0
	movlt	__v4, __v6
	movlt	__v3, __v5
|L..248|
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|log10|
	add	__v2, __sp, #64
	ldmia	__v2, {__v3-__v4}
	ldr	__ip, [__fp, #16]
	adr	__a3, |L..254|+48
	ldmia	__a3, {__a3-__a4}
	add	__v1, __ip, #24
	bl	|__muldf3|
	stmia	__v1, {__a1-__a2}
	mov	__a2, __v4
	mov	__a1, __v3
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__gedf2|
	cmp	__a1, #0
	movlt	__v4, __v6
	movlt	__v3, __v5
|L..249|
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|log10|
	adr	__a3, |L..254|+48
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|__truncdfsf2|
	ldr	__lr, [__fp, #16]
	str	__a1, [__lr, #32]	; float
	b	|L..253|
|L..255|
	ALIGN
|L..254|
	DCD	33244
	DCD	|pretab|
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD	|pow20|
	DCD	|pow43|
	DCD &3fe43958, &10624dd3	; double 6.32000000000000006217e-1
	DCD &3fd78d4f, &df3b645a	; double 3.67999999999999993783e-1
	DCD &3bc79ca1, &c924223	; double 9.99999999999999945153e-21
	DCD &40240000, &0	; double 1.00000000000000000000e1
	DCD &3ff00000, &0	; double 1.00000000000000000000e0
|L..253|
	ldr	__a1, [__sp, #28]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}

 EXPORT |quantize_xrpow|
|quantize_xrpow|
 stmfd r13!, {r4 - r11, r14}
 mov r11, r1
 mov r12, r0
 mov r10, #576

 orrs r4, r3, r2, lsl #1
 beq xrskip2
 mov r4, r2, lsl #11
 mov r2, r2, lsr #20
 orr r4, r4, r3, lsr #21
 add r2, r2, #0x3800
 orr r4, r4, #1<<31
xrskip2
  ldr r9, adj43_locate
 stmfd r13!, {r2, r4}   ; ISTEP

|L..591n|
 ldmia r12!, {r0, r2}   ; ldfd f3, [r12], #8
 orrs r1, r2, r0, lsl #1
 beq xrskip3
 ldmia r13, {r3, r4}    ; f0 = ISTEP
 orrs r1, r3, r4, lsl #1
 beq xrskip3
 mov r1, r0, lsl #11
 mov r0, r0, lsr #20    ; r0 is exponent bits
 orr r1, r1, r2, lsr #21 ; r1 is mantissa bits
 orr r1, r1, #1<<31     ; set hidden bit
 umull r2, r1, r4, r1   ; mufs f3, f3, f0
 add r0, r0, r3
 add r0, r0, #2
 cmp r1, #0
 bmi xrskip1
 adds r2, r2, r2        ; if not normalised, shift up by one
 adcs r1, r1, r1
 sub r0, r0, #1
xrskip1
 rsb r6, r0, #0x4100    ; fixz r6, f3...
 sub r8, r6, #0xE2
 movs r3, r8, lsr #5
 biceq r8, r8, r3, lsl #5
 moveq r6, r1, lsr r8
  addeq r7, r9, r6, lsl #3
 movne r7, r9
 _ldfd2  , , r7         ; ldfd f1, |adj43| + (8 * f3)
 bl |mech_adfs|         ; adfs f3, f3, f1
xrskip3_back
 bic r3, r0, #3<<30     ; fixz r6, f3...
 rsbs r6, r3, #0x4100
 sub r8, r6, #0xE2
 movs r7, r8, lsr #5
 bic r8, r8, r7, lsl #5
 moveq r6, r1, lsr r8
 movne r6, #0
  str r6, [r11], #4
  subs r10, r10, #1
  bgt |L..591n|

 add r13, r13, #8       ; adjust sp
 ldmfd r13!, {r4 - r11, r15}^

xrskip3
 _ldfd   , , r9         ; ldfd f3, |adj43|
 b xrskip3_back

adj43_locate dcd |adj43|


|L..262|
	DCD	|adj43|
	AREA |Common$$pow43|, DATA, COMMON
|pow43|
	% 65664	; size=65664
	EXPORT	|pow43|
	AREA |Common$$adj43|, DATA, COMMON
|adj43|
	% 65664	; size=65664
	EXPORT	|adj43|
	AREA |Common$$adj43asm|, DATA, COMMON
|adj43asm|
	% 65664	; size=65664
	EXPORT	|adj43asm|
	AREA |Common$$pow20|, DATA, COMMON
|pow20|
	% 2640	; size=2640
	EXPORT	|pow20|
	AREA |Common$$ipow20|, DATA, COMMON
|ipow20|
	% 2640	; size=2640
	EXPORT	|ipow20|
	AREA |C$$code2|, CODE, READONLY


 AREA |C$$code2|, CODE, READONLY
 ALIGN
 EXPORT |ms_convert|
|ms_convert|
 stmfd r13!, {r4 - r11, r14}
 sub r13, r13, #4*12
 mov r9, r13
 mov r11, r0
 mov r12, r1
 adrl r4, |L..357|
 ldmia r4, {r3 - r5}
 _fsave f0, {r3 - r5}   ; f0 = 1/sqrt(2)
 mov r10, #576

|L..79|
 _ldfd f3, r12, #0      ; ldfd f3, [r12, #0]
 _ldfd2 f2, r12, #4608  ; ldfd f2, [r12, #4608]
 _adfd   ,   ,          ; adfd f1, f3, f2
 _mufd   ,   , f0       ; mufd f1, f1, f0
 _stfd   , r11, #0      ; stfd f1, [r11, #0]
 _sufd   , f3, f2       ; sufd f1, f3, f2
 _mufd   ,   , f0       ; mufd f1, f1, f0
 _stfd   , r11, #4608   ; stfd f1, [r11, #4608]
 subs r10, r10, #1
 add r11, r11, #8
 add r12, r12, #8
 bgt |L..79|

 add r13, r13, #4*12
 ldmfd r13!, {r4 - r11, r15}^

|L..357|
 DCD &3FFE, &B504F333, &F9DE6485 ; long double 1/sqrt(2)


 EXPORT |quantize_xrpow_ISO|
|quantize_xrpow_ISO|
 stmfd r13!, {r3 - r9, r14}
  sub r13, r13, #2*12    ; range of fp regs actually used: f0 - f1
  mov r9, r13
 stmia r9, {r2, r3}
 _ldfd2 f0, , r9        ; f0 = ISTEP
 adr r7, |L..637n|
 _ldfd2 f1, , r7        ; ldfd f1, [r7]
 mov r2, #576

|L..600n|
  stmfd r13!, {r0 - r2}
 _ldfd   , , r0         ; ldfd f2, [r0]
 _fmls   ,   , f0       ; fmls f2, f2, f0
 _adfs   ,   , f1       ; adfs f2, f2, f1
 bic r3, r0, #3<<30
 bl |do_fix|            ; fixz r6, f2
  ldmfd r13!, {r0 - r2}
 add r0, r0, #8
 str r6, [r1], #4
 subs r2, r2, #1
 bgt |L..600n|

  add r13, r13, #2*12   ; adjust sp
 ldmfd r13!, {r3 - r9, r15}^

|L..637n|
 DCD &3fd9f212, &d77318fc ; double 4.05399999999999982592e-1



	EXPORT	|ATHmdct|
|ATHmdct|
	; args = 0, pretend = 0, frame = 0, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	mov	__v3, __a1
	mov	__a1, __a2
	mov	__a2, __a3
	mov	__a3, __v3
	ldr	__v1, [__v3, #232]
	bl	|ATHformula|
	ldr	__ip, |L..277|
	ldr	__a3, [__v1, __ip]
	mov	__v2, __a2
	mov	__v1, __a1
	cmp	__a3, #0
	adr	__a3, |L..277|+4
	ldmia	__a3, {__a3-__a4}
	bne	|L..276|
	adr	__a3, |L..277|+12
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
|L..276|
	bl	|__subdf3|
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__a1, [__v3, #172]	; float
	bl	|__extendsfdf2|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	adr	__a3, |L..277|+20
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..277|+28
	ldmia	__a1, {__a1-__a2}
	ldmea	__fp, {__v1, __v2, __v3, __fp, __sp, __lr}
	b	|pow|
|L..278|
	ALIGN
|L..277|
	DCD	227012
	DCD &40590000, &0	; double 1.00000000000000000000e2
	DCD &405c8000, &0	; double 1.14000000000000000000e2
	DCD &3fb99999, &9999999a	; double 1.00000000000000005551e-1
	DCD &40240000, &0	; double 1.00000000000000000000e1
	ALIGN
	EXPORT	|penalties|
|penalties|
	; args = 0, pretend = 0, frame = 0, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	mov	__v2, __a2
	mov	__v1, __a1
	adr	__a3, |L..279|
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__muldf3|
	adr	__a3, |L..279|+8
	ldmia	__a3, {__a3-__a4}
	bl	|__adddf3|
	ldmea	__fp, {__v1, __v2, __fp, __sp, __lr}
	b	|log|
|L..280|
	ALIGN
|L..279|
	DCD &3fe43958, &10624dd3	; double 6.32000000000000006217e-1
	DCD &3fd78d4f, &df3b645a	; double 3.67999999999999993783e-1
	END
