;->s.sswi2


        GBLL    names
names   SETL    {TRUE}



SWI_OP        * &EF000000 ; SWIAL opcode
XOS_MASK      * &00020000 ; mask to make a swi a RISC OS V-error SWI

; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Register names

r0 RN 0
r1 RN 1
r2 RN 2
r3 RN 3
r4 RN 4
r5 RN 5
r6 RN 6
r7 RN 7
r8 RN 8
r9 RN 9
r10 RN 10
r11 RN 11
r12 RN 12
r13 RN 13
r14 RN 14
r15 RN 15



a1 RN 0
a2 RN 1
a3 RN 2
a4 RN 3
v1 RN 4
v2 RN 5
v3 RN 6
v4 RN 7
v5 RN 8
v6 RN 9
sl RN 10
fp RN 11
ip RN 12
sp RN 13
lk RN 14
lr RN 14
pc RN 15



        EXPORT  |ss_swix2|

        AREA    |C$$code|, CODE, READONLY

|v$codesegment|


; os_error *ss_swix(int swicode,int r0,int r1,int r2);

; In    a1 contains swi number, a2 points to ARM register structure

 [ names
swixlabel
        DCB     "ss_swix", 0
        ALIGN
swixlength * . - swixlabel
        DCD     &FF000000 + swixlength
 ]

ss_swix2 STMDB   sp!, {v1-v6, lk}

        ORR     a1, a1, #SWI_OP         ; make into SWI operation
        ORR     a1, a1, #XOS_MASK       ; make a SWI of V-error type

        ADR     v1, xexit_sequence
        LDMIA   v1,      {v2,v3,v4,v5}
        STMDB   sp!, {a1, v2,v3,v4,v5} ; copy SWI and exit code onto stack

        MOV     a1,a2
        MOV     a2,a3
        MOV     a3,a4

        MOV     pc, sp                  ; and jump to the sequence

;       SWI     Xwhatever               ; <- sp
xexit_sequence

        MOV     a1,a1
        MOV     a1,a1
        ADD     sp,sp,#3*4
        LDMIA   sp!, {a2, a3, v1-v6, pc}^
                                        ; a2, a3 are junk (ADD and LDM)
                                        ; Note: CAN NOT move stack past LDM
                                        ; before instruction executes

        END
