@----------------------------------------------------------------------------
@
@ \Source /usr/local/cvsroot/gccsdk/unixlib/source/scl/_memchk.s,v $
@ \Date: 2002/02/14 15:5636 $
@ \Revision 1.3 $
@ \State Exp $
@ \Author admin $
@
@----------------------------------------------------------------------------

	.include	"clib/unixlib/asm_dec.s"


	.global	_rd1chk
	.global	_rd2chk
	.global	_rd4chk
	.global	__rt_rd1chk
	.global	__rt_rd2chk
	.global	__rt_rd4chk
	.global	_wr1chk
	.global	_wr2chk
	.global	_wr4chk
	.global	__rt_wr1chk
	.global	__rt_wr2chk
	.global	__rt_wr4chk

__rt_rd1chk:
_rd1chk:
	BIC	a1, a1, #1 	@ Ensure address is half word aligned
__rt_rd2chk:
_rd2chk:
	TST	a1, #1
	BNE	__rwNsegv
	BIC	a1, a1, #2 @ Ensure address is full word aligned
__rt_rd4chk:
_rd4chk:
	TST	a1, #2
	BNE	__rwNsegv

	LDR	a2, =__base
	LDR	a2, [a2]
__rwNchk:
	CMP	a1, a2
	BLO	__rwNsegv
	LDR	a2, =__break
	LDR	a2, [a2]
	CMP	a1, a2
	return	LO, pc, lr
	LDR	a2, =__stack
	LDR	a2, [a2]
	CMP	a1, a2
	BLO	__rwNsegv
	LDR	a2, =__himem
	LDR	a2, [a2]
	CMP	a1, a2
	return	LO, pc, lr
__rwNsegv:
	MOV	a1, #SIGSEGV
	B	raise

__rt_wr1chk:
_wr1chk:
	BIC	a1, a1, #1	@ Ensure address is half word aligned
__rt_wr2chk:
_wr2chk:
	TST	a1, #1
	BNE	__rwNsegv
	BIC	a1, a1, #2	@ Ensure address is full word aligned

__rt_wr4chk:
_wr4chk:
	TST	a1,#2
	BNE	__rwNsegv

	LDR	a2,=__rwbase
	LDR	a2,[a2]
	B	__rwNchk


