; Generated by gcc 2.95.4 20010319 (prerelease) [gccsdk 20020112] for ARM/RISC OS
__r0	RN	0
__r1	RN	1
__r2	RN	2
__r3	RN	3
__r4	RN	4
__r5	RN	5
__r6	RN	6
__r7	RN	7
__r8	RN	8
__r9	RN	9
__r10	RN	10
__r11	RN	11
__r12	RN	12
__r13	RN	13
__r14	RN	14
__r15	RN	15
__a1	RN	0
__a2	RN	1
__a3	RN	2
__a4	RN	3
__v1	RN	4
__v2	RN	5
__v3	RN	6
__v4	RN	7
__v5	RN	8
__v6	RN	9
__sl	RN	10
__fp	RN	11
__ip	RN	12
__sp	RN	13
__lr	RN	14
__pc	RN	15
__f0	FN	0
__f1	FN	1
__f2	FN	2
__f3	FN	3
__f4	FN	4
__f5	FN	5
__f6	FN	6
__f7	FN	7
	AREA |C$$code1|, CODE, READONLY
|gcc2_compiled.|
	AREA |C$$data1|, DATA
	ALIGN
	DCB &61, &76, &5f, &00
	ALIGN
	DCD	-16777212
|av_|
	KEEP |av_|
	DCD	0
	DCD	0
	DCD	|av_|
	DCD	|av_|
	DCD	|av_|+8
	DCD	|av_|+8
	DCD	|av_|+16
	DCD	|av_|+16
	DCD	|av_|+24
	DCD	|av_|+24
	DCD	|av_|+32
	DCD	|av_|+32
	DCD	|av_|+40
	DCD	|av_|+40
	DCD	|av_|+48
	DCD	|av_|+48
	DCD	|av_|+56
	DCD	|av_|+56
	DCD	|av_|+64
	DCD	|av_|+64
	DCD	|av_|+72
	DCD	|av_|+72
	DCD	|av_|+80
	DCD	|av_|+80
	DCD	|av_|+88
	DCD	|av_|+88
	DCD	|av_|+96
	DCD	|av_|+96
	DCD	|av_|+104
	DCD	|av_|+104
	DCD	|av_|+112
	DCD	|av_|+112
	DCD	|av_|+120
	DCD	|av_|+120
	DCD	|av_|+128
	DCD	|av_|+128
	DCD	|av_|+136
	DCD	|av_|+136
	DCD	|av_|+144
	DCD	|av_|+144
	DCD	|av_|+152
	DCD	|av_|+152
	DCD	|av_|+160
	DCD	|av_|+160
	DCD	|av_|+168
	DCD	|av_|+168
	DCD	|av_|+176
	DCD	|av_|+176
	DCD	|av_|+184
	DCD	|av_|+184
	DCD	|av_|+192
	DCD	|av_|+192
	DCD	|av_|+200
	DCD	|av_|+200
	DCD	|av_|+208
	DCD	|av_|+208
	DCD	|av_|+216
	DCD	|av_|+216
	DCD	|av_|+224
	DCD	|av_|+224
	DCD	|av_|+232
	DCD	|av_|+232
	DCD	|av_|+240
	DCD	|av_|+240
	DCD	|av_|+248
	DCD	|av_|+248
	DCD	|av_|+256
	DCD	|av_|+256
	DCD	|av_|+264
	DCD	|av_|+264
	DCD	|av_|+272
	DCD	|av_|+272
	DCD	|av_|+280
	DCD	|av_|+280
	DCD	|av_|+288
	DCD	|av_|+288
	DCD	|av_|+296
	DCD	|av_|+296
	DCD	|av_|+304
	DCD	|av_|+304
	DCD	|av_|+312
	DCD	|av_|+312
	DCD	|av_|+320
	DCD	|av_|+320
	DCD	|av_|+328
	DCD	|av_|+328
	DCD	|av_|+336
	DCD	|av_|+336
	DCD	|av_|+344
	DCD	|av_|+344
	DCD	|av_|+352
	DCD	|av_|+352
	DCD	|av_|+360
	DCD	|av_|+360
	DCD	|av_|+368
	DCD	|av_|+368
	DCD	|av_|+376
	DCD	|av_|+376
	DCD	|av_|+384
	DCD	|av_|+384
	DCD	|av_|+392
	DCD	|av_|+392
	DCD	|av_|+400
	DCD	|av_|+400
	DCD	|av_|+408
	DCD	|av_|+408
	DCD	|av_|+416
	DCD	|av_|+416
	DCD	|av_|+424
	DCD	|av_|+424
	DCD	|av_|+432
	DCD	|av_|+432
	DCD	|av_|+440
	DCD	|av_|+440
	DCD	|av_|+448
	DCD	|av_|+448
	DCD	|av_|+456
	DCD	|av_|+456
	DCD	|av_|+464
	DCD	|av_|+464
	DCD	|av_|+472
	DCD	|av_|+472
	DCD	|av_|+480
	DCD	|av_|+480
	DCD	|av_|+488
	DCD	|av_|+488
	DCD	|av_|+496
	DCD	|av_|+496
	DCD	|av_|+504
	DCD	|av_|+504
	DCD	|av_|+512
	DCD	|av_|+512
	DCD	|av_|+520
	DCD	|av_|+520
	DCD	|av_|+528
	DCD	|av_|+528
	DCD	|av_|+536
	DCD	|av_|+536
	DCD	|av_|+544
	DCD	|av_|+544
	DCD	|av_|+552
	DCD	|av_|+552
	DCD	|av_|+560
	DCD	|av_|+560
	DCD	|av_|+568
	DCD	|av_|+568
	DCD	|av_|+576
	DCD	|av_|+576
	DCD	|av_|+584
	DCD	|av_|+584
	DCD	|av_|+592
	DCD	|av_|+592
	DCD	|av_|+600
	DCD	|av_|+600
	DCD	|av_|+608
	DCD	|av_|+608
	DCD	|av_|+616
	DCD	|av_|+616
	DCD	|av_|+624
	DCD	|av_|+624
	DCD	|av_|+632
	DCD	|av_|+632
	DCD	|av_|+640
	DCD	|av_|+640
	DCD	|av_|+648
	DCD	|av_|+648
	DCD	|av_|+656
	DCD	|av_|+656
	DCD	|av_|+664
	DCD	|av_|+664
	DCD	|av_|+672
	DCD	|av_|+672
	DCD	|av_|+680
	DCD	|av_|+680
	DCD	|av_|+688
	DCD	|av_|+688
	DCD	|av_|+696
	DCD	|av_|+696
	DCD	|av_|+704
	DCD	|av_|+704
	DCD	|av_|+712
	DCD	|av_|+712
	DCD	|av_|+720
	DCD	|av_|+720
	DCD	|av_|+728
	DCD	|av_|+728
	DCD	|av_|+736
	DCD	|av_|+736
	DCD	|av_|+744
	DCD	|av_|+744
	DCD	|av_|+752
	DCD	|av_|+752
	DCD	|av_|+760
	DCD	|av_|+760
	DCD	|av_|+768
	DCD	|av_|+768
	DCD	|av_|+776
	DCD	|av_|+776
	DCD	|av_|+784
	DCD	|av_|+784
	DCD	|av_|+792
	DCD	|av_|+792
	DCD	|av_|+800
	DCD	|av_|+800
	DCD	|av_|+808
	DCD	|av_|+808
	DCD	|av_|+816
	DCD	|av_|+816
	DCD	|av_|+824
	DCD	|av_|+824
	DCD	|av_|+832
	DCD	|av_|+832
	DCD	|av_|+840
	DCD	|av_|+840
	DCD	|av_|+848
	DCD	|av_|+848
	DCD	|av_|+856
	DCD	|av_|+856
	DCD	|av_|+864
	DCD	|av_|+864
	DCD	|av_|+872
	DCD	|av_|+872
	DCD	|av_|+880
	DCD	|av_|+880
	DCD	|av_|+888
	DCD	|av_|+888
	DCD	|av_|+896
	DCD	|av_|+896
	DCD	|av_|+904
	DCD	|av_|+904
	DCD	|av_|+912
	DCD	|av_|+912
	DCD	|av_|+920
	DCD	|av_|+920
	DCD	|av_|+928
	DCD	|av_|+928
	DCD	|av_|+936
	DCD	|av_|+936
	DCD	|av_|+944
	DCD	|av_|+944
	DCD	|av_|+952
	DCD	|av_|+952
	DCD	|av_|+960
	DCD	|av_|+960
	DCD	|av_|+968
	DCD	|av_|+968
	DCD	|av_|+976
	DCD	|av_|+976
	DCD	|av_|+984
	DCD	|av_|+984
	DCD	|av_|+992
	DCD	|av_|+992
	DCD	|av_|+1000
	DCD	|av_|+1000
	DCD	|av_|+1008
	DCD	|av_|+1008
	DCD	|av_|+1016
	DCD	|av_|+1016
	ALIGN
	DCB &74, &72, &69, &6d
	DCB &5f, &74, &68, &72
	DCB &65, &73, &68, &6f
	DCB &6c, &64, &00
	ALIGN
	DCD	-16777200
|trim_threshold|
	KEEP |trim_threshold|
	DCD	131072
	ALIGN
	DCB &74, &6f, &70, &5f
	DCB &70, &61, &64, &00
	ALIGN
	DCD	-16777208
|top_pad|
	KEEP |top_pad|
	DCD	0
	ALIGN
	DCB &6e, &5f, &6d, &6d
	DCB &61, &70, &73, &5f
	DCB &6d, &61, &78, &00
	ALIGN
	DCD	-16777204
|n_mmaps_max|
	KEEP |n_mmaps_max|
	DCD	64
	ALIGN
	DCB &6d, &6d, &61, &70
	DCB &5f, &74, &68, &72
	DCB &65, &73, &68, &6f
	DCB &6c, &64, &00
	ALIGN
	DCD	-16777200
|mmap_threshold|
	KEEP |mmap_threshold|
	DCD	131072
	ALIGN
	DCB &73, &62, &72, &6b
	DCB &5f, &62, &61, &73
	DCB &65, &00
	ALIGN
	DCD	-16777204
|sbrk_base|
	KEEP |sbrk_base|
	DCD	-1
	ALIGN
	DCB &6d, &61, &78, &5f
	DCB &73, &62, &72, &6b
	DCB &65, &64, &5f, &6d
	DCB &65, &6d, &00
	ALIGN
	DCD	-16777200
|max_sbrked_mem|
	KEEP |max_sbrked_mem|
	DCD	0
	ALIGN
	DCB &6d, &61, &78, &5f
	DCB &74, &6f, &74, &61
	DCB &6c, &5f, &6d, &65
	DCB &6d, &00
	ALIGN
	DCD	-16777200
|max_total_mem|
	KEEP |max_total_mem|
	DCD	0
	ALIGN
	DCB &63, &75, &72, &72
	DCB &65, &6e, &74, &5f
	DCB &6d, &61, &6c, &6c
	DCB &69, &6e, &66, &6f
	DCB &00
	ALIGN
	DCD	-16777196
|current_mallinfo|
	KEEP |current_mallinfo|
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	ALIGN
	DCB &6e, &5f, &6d, &6d
	DCB &61, &70, &73, &00
	ALIGN
	DCD	-16777208
|n_mmaps|
	KEEP |n_mmaps|
	DCD	0
	ALIGN
	DCB &6d, &61, &78, &5f
	DCB &6e, &5f, &6d, &6d
	DCB &61, &70, &73, &00
	ALIGN
	DCD	-16777204
|max_n_mmaps|
	KEEP |max_n_mmaps|
	DCD	0
	ALIGN
	DCB &6d, &6d, &61, &70
	DCB &70, &65, &64, &5f
	DCB &6d, &65, &6d, &00
	ALIGN
	DCD	-16777204
|mmapped_mem|
	KEEP |mmapped_mem|
	DCD	0
	ALIGN
	DCB &6d, &61, &78, &5f
	DCB &6d, &6d, &61, &70
	DCB &70, &65, &64, &5f
	DCB &6d, &65, &6d, &00
	ALIGN
	DCD	-16777200
|max_mmapped_mem|
	KEEP |max_mmapped_mem|
	DCD	0
	AREA |C$$code2|, CODE, READONLY
	ALIGN
	DCB &6d, &6d, &61, &70
	DCB &5f, &63, &68, &75
	DCB &6e, &6b, &00
	ALIGN
	DCD	-16777204
|mmap_chunk|
	KEEP |mmap_chunk|
	; args = 0, pretend = 0, frame = 8, alloca = 0
	; frame_needed = 1, anonymous_args = 0, regs_live[14] = 0
	; nonlocal_label = 0, nonlocal_goto = 0, clobbers lr = 1
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	IMPORT	|__rt_stkovf_split_small|
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #8
	ldr	__v3, |L..10|
	ldr	__ip, |L..10|+4
	mov	__v1, __a1
	ldr	__a4, [__v3, #0]
	mov	__a2, #4080
	ldr	__a3, [__ip, #0]
	add	__a2, __a2, #15
	cmp	__a4, __a3
	bcc	|L..3|
|L..9|
	mov	__a1, #0
	ldmea	__fp, {__v1, __v2, __v3, __fp, __sp, __pc}
|L..3|
	add	__ip, __v1, #4096
	add	__ip, __ip, #3
	mvn	__a3, #0
	str	__a3, [__sp, #0]
	bic	__v1, __ip, __a2
	mov	__v2, #0
	str	__v2, [__sp, #4]
	mov	__a1, __v2
	mov	__a2, __v1
	add	__a3, __a3, #7
	mov	__a4, #2
	bl	|mmap|
	mov	__a2, __a1
	cmn	__a2, #1
	beq	|L..9|
	ldr	__a4, |L..10|+8
	ldr	__ip, [__v3, #0]
	ldr	__a3, [__a4, #0]
	add	__ip, __ip, #1
	str	__ip, [__v3, #0]
	cmp	__ip, __a3
	strhi	__ip, [__a4, #0]
|L..5|
	str	__v2, [__a2, #0]
	orr	__ip, __v1, #2
	str	__ip, [__a2, #4]
	ldr	__a4, |L..10|+12
	ldr	__lr, |L..10|+16
	ldr	__ip, [__a4, #0]
	ldr	__a3, [__lr, #0]
	add	__a1, __ip, __v1
	cmp	__a1, __a3
	str	__a1, [__a4, #0]
	strhi	__a1, [__lr, #0]
|L..6|
	ldr	__ip, |L..10|+20
	ldr	__lr, |L..10|+24
	ldr	__a3, [__ip, #0]
	ldr	__a4, [__lr, #0]
	add	__a1, __a1, __a3
	cmp	__a1, __a4
	strhi	__a1, [__lr, #0]
|L..7|
	mov	__a1, __a2
	ldmea	__fp, {__v1, __v2, __v3, __fp, __sp, __pc}
|L..11|
	ALIGN
|L..10|
	DCD	|n_mmaps|
	DCD	|n_mmaps_max|
	DCD	|max_n_mmaps|
	DCD	|mmapped_mem|
	DCD	|max_mmapped_mem|
	DCD	|current_mallinfo|
	DCD	|max_total_mem|
	ALIGN
	DCB &6d, &75, &6e, &6d
	DCB &61, &70, &5f, &63
	DCB &68, &75, &6e, &6b
	DCB &00
	ALIGN
	DCD	-16777200
|munmap_chunk|
	KEEP |munmap_chunk|
	; args = 0, pretend = 0, frame = 0, alloca = 0
	; frame_needed = 1, anonymous_args = 0, regs_live[14] = 0
	; nonlocal_label = 0, nonlocal_goto = 0, clobbers lr = 0
	; I don't think this function clobbers lr
	ldr	__a3, |L..13|
	ldr	__ip, [__a3, #0]
	ldr	__a2, [__a1, #4]
	sub	__ip, __ip, #1
	str	__ip, [__a3, #0]
	ldr	__a4, |L..13|+4
	ldr	__a3, [__a1, #0]
	bic	__a2, __a2, #3
	ldr	__ip, [__a4, #0]
	add	__a2, __a2, __a3
	rsb	__ip, __a2, __ip
	str	__ip, [__a4, #0]
	rsb	__a1, __a3, __a1
	b	|munmap|
|L..14|
	ALIGN
|L..13|
	DCD	|n_mmaps|
	DCD	|mmapped_mem|
	ALIGN
	DCB &6d, &61, &6c, &6c
	DCB &6f, &63, &5f, &65
	DCB &78, &74, &65, &6e
	DCB &64, &5f, &74, &6f
	DCB &70, &00
	ALIGN
	DCD	-16777196
|malloc_extend_top|
	KEEP |malloc_extend_top|
	; args = 0, pretend = 0, frame = 0, alloca = 0
	; frame_needed = 1, anonymous_args = 0, regs_live[14] = 0
	; nonlocal_label = 0, nonlocal_goto = 0, clobbers lr = 1
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	IMPORT	|__rt_stkovf_split_small|
	bllt	|__rt_stkovf_split_small|
	ldr	__a2, |L..31|
	ldr	__ip, |L..31|+4
	ldr	__v6, |L..31|+8
	ldr	__v5, [__a2, #8]
	ldr	__a3, [__ip, #0]
	ldr	__a4, [__v6, #0]
	add	__a1, __a1, __a3
	add	__v3, __a1, #16
	ldr	__ip, [__v5, #4]
	cmn	__a4, #1
	bic	__v4, __ip, #3
	add	__v1, __v5, __v4
	addne	__ip, __a1, #4096
	addne	__ip, __ip, #15
	bicne	__v3, __ip, #4080
	bicne	__v3, __v3, #15
|L..16|
	mov	__a1, __v3
	bl	|sbrk|
	mov	__v2, __a1
	cmn	__v2, #1
	ldmeqea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
	cmp	__v2, __v1
	bcs	|L..17|
	ldr	__a3, |L..31|
	cmp	__v5, __a3
	ldmneea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..17|
	ldr	__ip, |L..31|+12
	ldr	__a3, [__ip, #0]
	cmp	__v2, __v1
	add	__a3, __a3, __v3
	str	__a3, [__ip, #0]
	bne	|L..19|
	ldr	__a4, |L..31|
	add	__a1, __v3, __v4
	ldr	__a3, [__a4, #8]
	orr	__ip, __a1, #1
	str	__ip, [__a3, #4]
	b	|L..20|
|L..19|
	ldr	__ip, [__v6, #0]
	cmn	__ip, #1
	streq	__v2, [__v6, #0]
|L..21|
	rsbne	__ip, __v1, __v2
	addne	__ip, __a3, __ip
	ldrne	__a3, |L..31|+12
	strne	__ip, [__a3, #0]
|L..22|
	add	__ip, __v2, #8
	ands	__a1, __ip, #7
	rsbne	__v1, __a1, #8
	addne	__v2, __v2, __v1
|L..23|
	moveq	__v1, __a1
|L..24|
	add	__ip, __v2, __v3
	mov	__ip, __ip, asl #20
	mov	__ip, __ip, lsr #20
	rsb	__ip, __ip, #4096
	add	__v1, __v1, __ip
	mov	__a1, __v1
	bl	|sbrk|
	cmn	__a1, #1
	ldmeqea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
	ldr	__a4, |L..31|
	str	__v2, [__a4, #8]
	ldr	__a4, |L..31|+12
	rsb	__ip, __v2, __a1
	ldr	__a3, [__a4, #0]
	add	__a1, __ip, __v1
	ldr	__ip, |L..31|
	add	__a3, __a3, __v1
	str	__a3, [__a4, #0]
	cmp	__v5, __ip
	orr	__ip, __a1, #1
	str	__ip, [__v2, #4]
	beq	|L..20|
	cmp	__v4, #15
	bhi	|L..27|
	ldr	__a4, |L..31|
	ldr	__a3, [__a4, #8]
	mov	__ip, #1
	str	__ip, [__a3, #4]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..27|
	sub	__ip, __v4, #12
	bic	__v4, __ip, #7
	mov	__a2, #4
	add	__a3, __v5, __v4
	mov	__a4, #5
	str	__a4, [__a3, __a2]
	add	__a3, __a3, __a2
	str	__a4, [__a3, #4]
	ldr	__ip, [__v5, #4]
	cmp	__v4, #15
	and	__ip, __ip, #1
	orr	__ip, __ip, __v4
	str	__ip, [__v5, #4]
	bls	|L..20|
	add	__a1, __v5, #8
	bl	|free|
|L..20|
	ldr	__ip, |L..31|+12
	ldr	__a3, |L..31|+16
	ldr	__a2, [__ip, #0]
	ldr	__ip, [__a3, #0]
	cmp	__a2, __ip
	strhi	__a2, [__a3, #0]
|L..29|
	ldr	__ip, |L..31|+20
	ldr	__a1, |L..31|+24
	ldr	__a3, [__ip, #0]
	ldr	__a4, [__a1, #0]
	add	__a3, __a3, __a2
	cmp	__a3, __a4
	strhi	__a3, [__a1, #0]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..32|
	ALIGN
|L..31|
	DCD	|av_|
	DCD	|top_pad|
	DCD	|sbrk_base|
	DCD	|current_mallinfo|
	DCD	|max_sbrked_mem|
	DCD	|mmapped_mem|
	DCD	|max_total_mem|
	ALIGN
	EXPORT	|malloc|
	DCB &6d, &61, &6c, &6c
	DCB &6f, &63, &00
	ALIGN
	DCD	-16777208
|malloc|
	; args = 0, pretend = 0, frame = 0, alloca = 0
	; frame_needed = 1, anonymous_args = 0, regs_live[14] = 0
	; nonlocal_label = 0, nonlocal_goto = 0, clobbers lr = 1
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	IMPORT	|__rt_stkovf_split_small|
	bllt	|__rt_stkovf_split_small|
	add	__a3, __a1, #11
	bic	__ip, __a3, #7
	cmp	__a3, #22
	movgt	__v4, __ip
	movle	__v4, #16
	cmp	__v4, __a1
	bcc	|L..129|
	cmp	__v4, #504
	bcs	|L..37|
	ldr	__ip, |L..130|
	mov	__v3, __v4, lsr #3
	add	__a2, __ip, __v3, asl #3
	ldr	__a1, [__a2, #12]
	cmp	__a1, __a2
	addeq	__a2, __a1, #8
	ldreq	__a1, [__a2, #12]
|L..38|
	cmp	__a1, __a2
	beq	|L..39|
	ldr	__a2, [__a1, #12]
	ldmib	__a1, {__ip, __lr}	; phole ldm
	str	__a2, [__lr, #12]
	str	__lr, [__a2, #8]
	mov	__a4, #4
	bic	__v1, __ip, #3
|L..126|
	add	__a3, __a1, __v1
	ldr	__ip, [__a3, __a4]
	add	__a1, __a1, #8
	orr	__ip, __ip, #1
	str	__ip, [__a3, __a4]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..39|
	add	__v3, __v3, #2
	b	|L..40|
|L..37|
	movs	__a3, __v4, lsr #9
	moveq	__v3, __v4, lsr #3
	beq	|L..42|
|L..41|
	cmp	__a3, #4
	movls	__ip, __v4, lsr #6
	addls	__v3, __ip, #56
	bls	|L..42|
|L..43|
	cmp	__a3, #20
	addls	__v3, __a3, #91
	bls	|L..42|
|L..45|
	cmp	__a3, #84
	movls	__ip, __v4, lsr #12
	addls	__v3, __ip, #110
	bls	|L..42|
|L..47|
	cmp	__a3, #340
	movls	__ip, __v4, lsr #15
	addls	__v3, __ip, #119
	bls	|L..42|
|L..49|
	mov	__ip, #1360
	add	__ip, __ip, #4
	cmp	__a3, __ip
	movls	__ip, __v4, lsr #18
	addls	__v3, __ip, #124
|L..51|
	movhi	__v3, #126
|L..42|
	ldr	__ip, |L..130|
	add	__lr, __ip, __v3, asl #3
	ldr	__a1, [__lr, #12]
	b	|L..125|
|L..57|
	cmp	__a4, #0
	bge	|L..121|
	ldr	__a1, [__a1, #12]
|L..125|
	cmp	__a1, __lr
	beq	|L..54|
	ldr	__ip, [__a1, #4]
	bic	__v1, __ip, #3
	rsb	__a4, __v4, __v1
	cmp	__a4, #15
	ble	|L..57|
	sub	__v3, __v3, #1
|L..54|
	add	__v3, __v3, #1
|L..40|
	ldr	__ip, |L..130|+4
	ldr	__a1, [__ip, #8]
	mov	__v6, __ip
	cmp	__a1, __ip
	beq	|L..61|
	ldr	__ip, [__a1, #4]
	bic	__v1, __ip, #3
	rsb	__a4, __v4, __v1
	cmp	__a4, #15
	ble	|L..62|
	orr	__ip, __v4, #1
	str	__ip, [__a1, #4]
|L..128|
	add	__a3, __a1, __v4
	str	__a3, [__v6, #12]
	str	__a3, [__v6, #8]
	str	__v6, [__a3, #12]
	str	__v6, [__a3, #8]
	orr	__ip, __a4, #1
	str	__ip, [__a3, #4]
	add	__a1, __a1, #8
	str	__a4, [__a3, __a4]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..62|
	str	__v6, [__v6, #12]
	cmp	__a4, #0
	str	__v6, [__v6, #8]
	movge	__a4, #4
	bge	|L..126|
|L..63|
	cmp	__v1, #512
	bcs	|L..64|
	mov	__v2, __v1, lsr #3
	sub	__a4, __v6, #8
	mov	__a2, __v2, lsr #2
	ldr	__ip, [__a4, #4]
	mov	__a3, #1
	orr	__ip, __ip, __a3, asl __a2
	str	__ip, [__a4, #4]
	add	__a2, __a4, __v2, asl #3
	ldr	__lr, [__a2, #8]
	b	|L..79|
|L..64|
	movs	__a2, __v1, lsr #9
	moveq	__v2, __v1, lsr #3
	beq	|L..67|
|L..66|
	cmp	__a2, #4
	movls	__ip, __v1, lsr #6
	addls	__v2, __ip, #56
	bls	|L..67|
|L..68|
	cmp	__a2, #20
	addls	__v2, __a2, #91
	bls	|L..67|
|L..70|
	cmp	__a2, #84
	movls	__ip, __v1, lsr #12
	addls	__v2, __ip, #110
	bls	|L..67|
|L..72|
	cmp	__a2, #340
	movls	__ip, __v1, lsr #15
	addls	__v2, __ip, #119
	bls	|L..67|
|L..74|
	mov	__ip, #1360
	add	__ip, __ip, #4
	cmp	__a2, __ip
	movls	__ip, __v1, lsr #18
	addls	__v2, __ip, #124
|L..76|
	movhi	__v2, #126
|L..67|
	ldr	__a4, |L..130|
	add	__a2, __a4, __v2, asl #3
	ldr	__lr, [__a2, #8]
	cmp	__lr, __a2
	bne	|L..127|
	mov	__ip, __v2, lsr #2
	ldr	__a3, [__a4, #4]
	mov	__a4, #1
	orr	__a3, __a3, __a4, asl __ip
	ldr	__ip, |L..130|
	str	__a3, [__ip, #4]
	b	|L..79|
|L..82|
	ldr	__lr, [__lr, #8]
	cmp	__lr, __a2
	beq	|L..81|
|L..127|
	ldr	__ip, [__lr, #4]
	bic	__ip, __ip, #3
	cmp	__v1, __ip
	bcc	|L..82|
|L..81|
	ldr	__a2, [__lr, #12]
|L..79|
	str	__a2, [__a1, #12]
	str	__lr, [__a1, #8]
	str	__a1, [__a2, #8]
	str	__a1, [__lr, #12]
|L..61|
	cmp	__v3, #0
	addlt	__ip, __v3, #3
	movge	__ip, __v3
	mov	__ip, __ip, asr #2
	ldr	__a2, |L..130|
	mov	__a3, #1
	ldr	__a4, [__a2, #4]
	mov	__a3, __a3, asl __ip
	cmp	__a3, __a4
	bhi	|L..85|
	tst	__a3, __a4
	bne	|L..86|
	bic	__ip, __v3, #3
	add	__v3, __ip, #4
	mov	__a3, __a3, asl #1
	tst	__a3, __a4
	bne	|L..86|
	mov	__ip, __a4
|L..89|
	add	__v3, __v3, #4
	mov	__a3, __a3, asl #1
	tst	__a3, __ip
	beq	|L..89|
|L..86|
	ldr	__v5, |L..130|
|L..91|
	mov	__v2, __v3
	add	__a2, __v5, __v3, asl #3
	mov	__lr, __a2
|L..105|
	ldr	__a1, [__lr, #12]
	cmp	__a1, __lr
	beq	|L..98|
|L..100|
	ldr	__ip, [__a1, #4]
	bic	__v1, __ip, #3
	rsb	__a4, __v4, __v1
	cmp	__a4, #15
	bgt	|L..122|
	cmp	__a4, #0
	bge	|L..123|
	ldr	__a1, [__a1, #12]
	cmp	__a1, __lr
	bne	|L..100|
|L..98|
	add	__lr, __lr, #8
	add	__v3, __v3, #1
	tst	__v3, #3
	bne	|L..105|
|L..110|
	tst	__v2, #3
	beq	|L..124|
	sub	__a2, __a2, #8
	ldr	__ip, [__a2, #8]
	sub	__v2, __v2, #1
	cmp	__ip, __a2
	beq	|L..110|
|L..107|
	ldr	__ip, [__v5, #4]
	mov	__a3, __a3, asl #1
	cmp	__a3, __ip
	bhi	|L..85|
	cmp	__a3, #0
	beq	|L..85|
	tst	__a3, __ip
	bne	|L..91|
	ldr	__a4, |L..130|
	ldr	__ip, [__a4, #4]
|L..114|
	add	__v3, __v3, #4
	mov	__a3, __a3, asl #1
	tst	__a3, __ip
	beq	|L..114|
	b	|L..91|
|L..124|
	ldr	__ip, [__v5, #4]
	bic	__ip, __ip, __a3
	str	__ip, [__v5, #4]
	b	|L..107|
|L..131|
	ALIGN
|L..130|
	DCD	|av_|
	DCD	|av_|+8
|L..85|
	ldr	__ip, |L..132|
	ldr	__a3, [__ip, #8]
	ldr	__ip, [__a3, #4]
	bic	__ip, __ip, #3
	rsb	__a4, __v4, __ip
	cmp	__a4, #15
	bgt	|L..117|
	ldr	__ip, |L..132|+4
	ldr	__a3, [__ip, #0]
	cmp	__v4, __a3
	bcc	|L..118|
	mov	__a1, __v4
	bl	|mmap_chunk|
	cmp	__a1, #0
	add	__a1, __a1, #8
	ldmneea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..118|
	mov	__a1, __v4
	bl	|malloc_extend_top|
	ldr	__a2, |L..132|
	ldr	__a3, [__a2, #8]
	ldr	__ip, [__a3, #4]
	bic	__ip, __ip, #3
	rsb	__a4, __v4, __ip
	cmp	__a4, #15
	bgt	|L..117|
|L..129|
	mov	__a1, #0
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..121|
	ldr	__a2, [__a1, #12]
	ldr	__lr, [__a1, #8]
	str	__a2, [__lr, #12]
	str	__lr, [__a2, #8]
	mov	__a4, #4
	b	|L..126|
|L..122|
	orr	__ip, __v4, #1
	str	__ip, [__a1, #4]
	ldr	__a2, [__a1, #12]
	ldr	__lr, [__a1, #8]
	str	__a2, [__lr, #12]
	str	__lr, [__a2, #8]
	b	|L..128|
|L..123|
	mov	__a4, #4
	add	__a3, __a1, __v1
	ldr	__ip, [__a3, __a4]
	orr	__ip, __ip, #1
	str	__ip, [__a3, __a4]
	ldr	__a2, [__a1, #12]
	ldr	__lr, [__a1, #8]
	str	__a2, [__lr, #12]
	add	__a1, __a1, #8
	str	__lr, [__a2, #8]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..117|
	ldr	__ip, |L..132|
	ldr	__a1, [__ip, #8]
	orr	__ip, __v4, #1
	str	__ip, [__a1, #4]
	ldr	__a2, |L..132|
	add	__a3, __a1, __v4
	str	__a3, [__a2, #8]
	add	__a1, __a1, #8
	orr	__ip, __a4, #1
	str	__ip, [__a3, #4]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..133|
	ALIGN
|L..132|
	DCD	|av_|
	DCD	|mmap_threshold|
	ALIGN
	EXPORT	|free|
	DCB &66, &72, &65, &65
	DCB &00
	ALIGN
	DCD	-16777208
|free|
	; args = 0, pretend = 0, frame = 0, alloca = 0
	; frame_needed = 1, anonymous_args = 0, regs_live[14] = 0
	; nonlocal_label = 0, nonlocal_goto = 0, clobbers lr = 1
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	IMPORT	|__rt_stkovf_split_small|
	bllt	|__rt_stkovf_split_small|
	cmp	__a1, #0
	ldmeqea	__fp, {__v1, __v2, __v3, __v4, __v5, __fp, __sp, __pc}
	sub	__v2, __a1, #8
	ldr	__a2, [__v2, #4]
	ands	__lr, __a2, #2
	beq	|L..136|
	mov	__a1, __v2
	bl	|munmap_chunk|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __fp, __sp, __pc}
|L..136|
	bic	__v1, __a2, #1
	add	__v3, __v2, __v1
	ldr	__ip, [__v3, #4]
	ldr	__a4, |L..170|
	bic	__v4, __ip, #3
	ldr	__a3, [__a4, #8]
	mov	__v5, __a4
	cmp	__v3, __a3
	bne	|L..137|
	add	__v1, __v1, __v4
	tst	__a2, #1
	bne	|L..138|
	ldr	__a1, [__a1, #-8]
	rsb	__v2, __a1, __v2
	add	__a2, __v2, #8
	ldmia	__a2, {__a2, __lr}	; phole ldm
	str	__lr, [__a2, #12]
	add	__v1, __v1, __a1
	str	__a2, [__lr, #8]
|L..138|
	orr	__ip, __v1, #1
	str	__ip, [__v2, #4]
	ldr	__a3, |L..170|+4
	ldr	__ip, [__a3, #0]
	str	__v2, [__v5, #8]
	cmp	__v1, __ip
	ldmccea	__fp, {__v1, __v2, __v3, __v4, __v5, __fp, __sp, __pc}
	ldr	__ip, |L..170|+8
	ldr	__a1, [__ip, #0]
	bl	|malloc_trim|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __fp, __sp, __pc}
|L..137|
	mov	__a4, __lr
	tst	__a2, #1
	str	__v4, [__v3, #4]
	bne	|L..140|
	ldr	__a1, [__a1, #-8]
	add	__ip, __v5, #8
	rsb	__v2, __a1, __v2
	ldr	__a3, [__v2, #8]
	add	__v1, __v1, __