# When building with FPA support, use:
#  CDP={ne(coproc,1)}
#  LDC_STC={ne(coproc,1)}{ne(coproc,2)}
#  MRC_MCR={ne(coproc,1)}
# When building without FPA, just set the above to null

# A6.1
11100(:27)	IS_T16
0(:31)		IS_T16
10(:30)		IS_T16
110(:29)	IS_T16

# A6.3
111(op1:2)(op2:7)(:4)(op)(:15)	{eq(op1,3)} {eq(band(op2,0x67),0x07)}	UNDEFINED

# A6.3.1
#11110(:1)0(op:4)S(Rn:4)0(:3)(Rd:4)(:8)	{lnot(op)} {eq(Rd,15)} {lnot(S)}	UNPREDICTABLE # - leave it to the AND/EOR/ADD/SUB actions to detect these unpredictable states (as their individual pseudocode indicates)
#11110(:1)0(op:4)S(Rn:4)0(:3)(Rd:4)(:8)	{eq(op,4)} {eq(Rd,15)} {lnot(S)}	UNPREDICTABLE
11110(:1)0(op:4)S(Rn:4)0(:3)(Rd:4)(:8)	{eq(band(op,0xc),4)} {band(op,3)}	UNDEFINED
#11110(:1)0(op:4)S(Rn:4)0(:3)(Rd:4)(:8)	{eq(op,8)} {eq(Rd,15)} {lnot(S)}	UNPREDICTABLE
11110(:1)0(op:4)S(Rn:4)0(:3)(Rd:4)(:8)	{eq(op,9)}	UNDEFINED
11110(:1)0(op:4)S(Rn:4)0(:3)(Rd:4)(:8)	{eq(op,12)}	UNDEFINED
#11110(:1)0(op:4)S(Rn:4)0(:3)(Rd:4)(:8)	{eq(op,13)} {eq(Rd,15)} {lnot(S)}	UNPREDICTABLE
11110(:1)0(op:4)S(Rn:4)0(:3)(Rd:4)(:8)	{eq(op,15)}	UNDEFINED

# A6.3.3
11110(:1)1(op:5)(Rn:4)0(:15)	{band(op,1)}	UNDEFINED
11110(:1)1(op:5)(Rn:4)0(:15)	{eq(op,2)}	UNDEFINED
11110(:1)1(op:5)(Rn:4)0(:15)	{eq(op,6)}	UNDEFINED
11110(:1)1(op:5)(Rn:4)0(:15)	{eq(op,8)}	UNDEFINED
11110(:1)1(op:5)(Rn:4)0(:15)	{eq(band(op,15),14)}	UNDEFINED

# A6.3.4
11110(op:7)(:4)1(op1:3)(op2:4)(:8)	{lnot(op1)} {lt(op,0x7e)} {ge(op,0x78)}	UNDEFINED
11110(op:7)(:4)1(op1:3)(op2:4)(:8)	{eq(op1,2)} {ne(op,0x7f)} {ge(op,0x78)}	UNDEFINED
111100111010(:4)10(:1)0(:1)(op1:3)(op2:8)	{lnot(op1)} {gt(op2,4)} {lt(op2,0xf0)}	UNALLOCATED_HINT
111100111011(:4)10(:1)0(:4)(op:4)(:4)	{eq(op,3)}	UNDEFINED_IN_v7_ELSE_UNPREDICTABLE
111100111011(:4)10(:1)0(:4)(op:4)(:4)	{gt(op,6)}	UNDEFINED_IN_v7_ELSE_UNPREDICTABLE

# A6.3.6
1110100(op1:2)1(op2:2)(Rn:4)(:8)(op3:4)(:4)	{eq(op1,1)} {lt(op2,2)} {gt(op3,7)}	UNDEFINED
1110100(op1:2)1(op2:2)(Rn:4)(:8)(op3:4)(:4)	{eq(op1,1)} {lt(op2,2)} {eq(op3,6)}	UNDEFINED
1110100(op1:2)1(op2:2)(Rn:4)(:8)(op3:4)(:4)	{eq(op1,1)} {lnot(op2)} {lt(op3,4)}	UNDEFINED
1110100(op1:2)1(op2:2)(Rn:4)(:8)(op3:4)(:4)	{eq(op1,1)} {eq(op2,1)} {eq(band(op3,14),2)}	UNDEFINED

# A6.3.7
1111100(op1:2)101(Rn:4)(:4)(op2:6)(:6)	{gt(op1,1)}	UNDEFINED
1111100(op1:2)101(Rn:4)(:4)(op2:6)(:6)	{lnot(op1)} {ne(Rn,15)} {op2} {lt(op2,32)}	UNDEFINED
#1111100(op1:2)101(Rn:4)(:4)(op2:6)(:6)	{lnot(op1)} {ne(Rn,15)} {eq(band(op2,0x34),32)}	UNDEFINED # - covered by LDR, etc.

# A6.3.8
#1111100(op1:2)011(Rn:4)(Rt:4)(op2:6)(:6)	{lt(op1,2)} {eq(Rn,15)} {eq(Rt,15)}	UNPREDICTABLE # - leave it to PLD/etc. actions to detect these unpredictable states (as their individual pseudocode indicates)
1111100(op1:2)011(Rn:4)(Rt:4)(op2:6)(:6)	{ge(op1,2)} {eq(Rn,15)} {eq(Rt,15)}	UNALLOCATED_MEM_HINT
1111100(op1:2)011(Rn:4)(Rt:4)(op2:6)(:6)	{eq(op1,3)} {ne(Rn,15)} {eq(Rt,15)}	UNALLOCATED_MEM_HINT
1111100(op1:2)011(Rn:4)(Rt:4)(op2:6)(:6)	{lnot(band(op1,1))} {ne(Rn,15)} {op2} {lt(op2,32)}	UNDEFINED
#1111100(op1:2)011(Rn:4)(Rt:4)(op2:6)(:6)	{lnot(band(op1,1))} {ne(Rn,15)} {eq(band(op2,0x34),32)}	UNDEFINED # - covered by LDRH, etc.
#1111100(op1:2)011(Rn:4)(Rt:4)(op2:6)(:6)	{lnot(band(op1,1))} {ne(Rn,15)} {eq(Rt,15)} {lor(eq(band(op2,0x24),0x24),eq(band(op2,0x3c),0x38))}	UNPREDICTABLE # - leave it to LDRH/etc. actions to detect these unpredictable states (as their individual pseudocode indicates)
1111100(op1:2)011(Rn:4)(Rt:4)(op2:6)(:6)	{eq(op1,2)} {ne(Rn,15)} {eq(Rt,15)} {lor(lnot(op2),eq(band(op2,0x3c),0x30))}	UNALLOCATED_MEM_HINT

# A6.3.9
1111100(op1:2)001(Rn:4)(Rt:4)(op2:6)(:6)	{lnot(band(op1,1))} {ne(Rn,15)} {op2} {lt(op2,32)}	UNDEFINED
#1111100(op1:2)001(Rn:4)(Rt:4)(op2:6)(:6)	{lnot(band(op1,1))} {ne(Rn,15)} {eq(band(op2,0x34),32)}	UNDEFINED # - covered by LDRB, etc.
#1111100(op1:2)001(Rn:4)(Rt:4)(op2:6)(:6)	{lnot(band(op1,1))} {ne(Rn,15)} {eq(Rt,15)} {lor(eq(band(op2,0x24),0x24),eq(band(op2,0x3c),0x38))}	UNPREDICTABLE # - leave it to the LDRB/etc. actions to detect these unpredictable states (as their individual pseudocode indicates) 

# A6.3.10
11111000(op1:3)0(:8)(op2:6)(:6)	{eq(band(op1,3),3)}	UNDEFINED
11111000(op1:3)0(:8)(op2:6)(:6)	{lt(op1,3)} {op2} {lt(op2,32)}	UNDEFINED
#11111000(op1:3)0(:8)(op2:6)(:6)	{lt(op1,3)} {eq(band(op2,0x34),32)}	UNDEFINED # - covered by STRB, etc.

# A6.3.11
#1110101(op:4)S(Rn:4)(:4)(Rd:4)(:8)	{eq(Rd,15)} {S} {lor(lor(lnot(op),eq(op,4)),lor(eq(op,8),eq(op,13)))}	UNPREDICTABLE # - covered by TST, TEQ, etc.
1110101(op:4)S(Rn:4)(:4)(Rd:4)(:8)	{lor(lor(lor(eq(op,5),eq(op,7)),lor(eq(op,9),eq(op,12))),eq(op,15))}	UNDEFINED

# A6.3.12
11111010(op1:4)(Rn:4)(x:4)(:4)(op2:4)(:4)	{ne(x,15)}	UNDEFINED
11111010(op1:4)(Rn:4)1111(:4)(op2:4)(:4)	{lt(op1,8)} {op2} {lt(op2,8)}	UNDEFINED
11111010(op1:4)(Rn:4)1111(:4)(op2:4)(:4)	{eq(band(op1,14),6)} {ge(op2,8)}	UNDEFINED
11111010(op1:4)(Rn:4)1111(:4)(op2:4)(:4)	{ge(op1,8)} {ge(op2,12)}	UNDEFINED
11111010(op1:4)(Rn:4)1111(:4)(op2:4)(:4)	{ge(op1,12)} {eq(band(op2,12),8)}	UNDEFINED

# A6.3.13
111110101(op1:3)(:4)1111(:4)00(op2:2)(:4)	{eq(op2,3)}	UNDEFINED
111110101(op1:3)(:4)1111(:4)00(op2:2)(:4)	{ne(op2,3)} {eq(band(op1,3),3)}	UNDEFINED

# A6.3.14
111110101(op1:3)(:4)1111(:4)01(op2:2)(:4)	{eq(op2,3)}	UNDEFINED
111110101(op1:3)(:4)1111(:4)01(op2:2)(:4)	{ne(op2,3)} {eq(band(op1,3),3)}	UNDEFINED

# A6.3.15
1111101010(op1:2)(:4)1111(:4)10(op2:2)(:4)	{band(op1,2)} {op2}	UNDEFINED

# A6.3.16
111110110(op1:3)(:4)(Ra:4)(:4)(x:2)(op2:2)(:4)	{x}	UNDEFINED
111110110(op1:3)(:4)(Ra:4)(:4)00(op2:2)(:4)	{ne(op1,1)} {band(op2,2)}	UNDEFINED
111110110(op1:3)(:4)(Ra:4)(:4)00(op2:2)(:4)	{eq(op1,7)} {eq(op2,1)}	UNDEFINED

# A6.3.17
111110111(op1:3)(:4)(:8)(op2:4)(:4)	{lnot(band(op1,5))} {eq(op2,15)}	UNDEFINED
111110111(op1:3)(:4)(:8)(op2:4)(:4)	{eq(band(op1,5),1)} {lnot(op2)}	UNDEFINED
111110111(op1:3)(:4)(:8)(op2:4)(:4)	{lt(op1,4)} {op2} {ne(op2,15)}	UNDEFINED
111110111(op1:3)(:4)(:8)(op2:4)(:4)	{eq(op1,7)}	UNDEFINED
111110111(op1:3)(:4)(:8)(op2:4)(:4)	{eq(op1,4)} {op2} {lor(lt(op2,8),gt(op2,13))}	UNDEFINED
111110111(op1:3)(:4)(:8)(op2:4)(:4)	{eq(op1,5)} {ne(band(op2,14),12)}	UNDEFINED
111110111(op1:3)(:4)(:8)(op2:4)(:4)	{eq(op1,6)} {op2} {ne(op2,6)}	UNDEFINED

# A6.3.18
#111(:1)11(op1:6)(Rn:4)(:4)(coproc:4)(:3)(op)(:4)	{lt(op1,2)}	UNDEFINED # - covered by LDC/STC

# A8.8.1 ADC (immediate)
# T1 ARMv6T2 ARMv7
11110i01010S(Rn:4)0(imm3:3)(Rd:4)(imm8:8)	ADC_imm_T1

# A8.8.2 ADC (register)
# T2 ARMv6T2, ARMv7
11101011010S(Rn:4)(0)(imm3:3)(Rd:4)(imm2:2)(type:2)(Rm:4)	ADC_reg_T2

# A8.8.4 ADD (immmediate, Thumb)
# T3 ARMv6T2, ARMv7
11110i01000S(Rn:4)0(imm3:3)(Rd:4)(imm8:8)	{lor(ne(Rd,15),lnot(S))} {ne(Rn,13)}	ADD_imm_T3
# T4 ARMv6T2, ARMv7
11110i100000(Rn:4)0(imm3:3)(Rd:4)(imm8:8)	{lnot(BadReg(Rn))}	ADD_imm_T4

# A8.8.6 ADD (register, Thumb)
# T3 ARMv6T2, ARMv7
11101011000S(Rn:4)(0)(imm3:3)(Rd:4)(imm2:2)(type:2)(Rm:4)	{lor(ne(Rd,15),ne(S,1))} {ne(Rn,13)}	ADD_reg_T3

# A8.8.9 ADD (SP plus immediate)
# T3 ARMv6T2, ARMv7
11110i01000S11010(imm3:3)(Rd:4)(imm8:8)	{lor(ne(Rd,15),lnot(S))}	ADD_sp_imm_T3
# T4 ARMv6T2, ARMv7
11110i10000011010(imm3:3)(Rd:4)(imm8:8)	ADD_sp_imm_T4

# A8.8.10 ADD (SP plus register, Thumb)
# T3 ARMv6T2, ARMv7
11101011000S1101(0)(imm3:3)(Rd:4)(imm2:2)(type:2)(Rm:4)	{lnot(land(S,eq(Rd,15)))}	ADD_sp_reg_T3

# A8.8.12 ADR
# T2 ARMv6T2, ARMv7
11110i10101011110(imm3:3)(Rd:4)(imm8:8)	ADR_T2
# T3 ARMv6T2, ARMv7
11110i10000011110(imm3:3)(Rd:4)(imm8:8)	ADR_T3

# A8.8.13 AND (immediate)
# T1 ARMv6T2, ARMv7
11110i00000S(Rn:4)0(imm3:3)(Rd:4)(imm8:8)	{lor(ne(Rd,15),ne(S,1))}	AND_imm_T1

# A8.8.14 AND (register)
# T2 ARMv6T2, ARMv7
11101010000S(Rn:4)(0)(imm3:3)(Rd:4)(imm2:2)(type:2)(Rm:4)	{lor(ne(Rd,15),ne(S,1))}	AND_reg_T2

# A8.8.16 ASR (immediate)
# T2 ARMv6T2, ARMv7
11101010010S1111(0)(imm3:3)(Rd:4)(imm2:2)10(Rm:4)	ASR_imm_T2

# A8.8.17 ASR (register)
# T2 ARMv6T2, ARMv7
11111010010S(Rn:4)1111(Rd:4)0000(Rm:4)	ASR_reg_T2

# A8.8.18 B
# T3 ARMv6T2, ARMv7
11110S(cond:4)(imm6:6)10(J1)0(J2)(imm11:11)	{lt(cond,14)}	B_T3
# T4 ARMv6T2, ARMv7
11110S(imm10:10)10(J1)1(J2)(imm11:11)	B_T4

# A8.8.19 BFC
# T1 ARMv6T2, ARMv7
11110(0)11011011110(imm3:3)(Rd:4)(imm2:2)(0)(msb:5)	BFC_T1

# A8.8.20 BFI
# T1 ARMv6T2, ARMv7
11110(0)110110(Rn:4)0(imm3:3)(Rd:4)(imm2:2)(0)(msb:5)	{ne(Rn,15)}	BFI_T1

# A8.8.21 BIC (immediate)
# T1 ARMv6T2, ARMv7
11110i00001S(Rn:4)0(imm3:3)(Rd:4)(imm8:8)	BIC_T1

# A8.8.22 BIC (register)
# T2 ARMv6T2, ARMv7
11101010001S(Rn:4)(0)(imm3:3)(Rd:4)(imm2:2)(type:2)(Rm:4)	BIC_reg_T2

# A8.8.25 BL, BLX (immediate)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
11110S(imm10:10)11111(imm11:11)	BL_BLX_imm_T1a
# T1 ARMv6T2, ARMv7
11110S(imm10:10)11(J1)1(J2)(imm11:11)	{lnot(band(J1,J2))}	BL_BLX_imm_T1b

# A8.8.28 BXJ
# T1 ARMv6T2, ARMv7
111100111100(Rm:4)10(0)0(111100000000)	BXJ_T1

# A8.8.30 CDP, CDP2
# T1 ARMv6T2, ARMv7
11101110(opc1:4)(CRn:4)(CRd:4)(coproc:4)(opc2:3)0(CRm:4)	{ne(coproc,10)} {ne(coproc,11)} [CDP]	CDP_CDP2_T1
# T2 ARMv6T2, ARMv7
11111110(opc1:4)(CRn:4)(CRd:4)(coproc:4)(opc2:3)0(CRm:4)	CDP_CDP2_T2

# A8.8.32 CLREX
# T1 ARMv7
111100111011(1111)10(0)0(1111)0010(1111)	CLREX_T1

# A8.8.33 CLZ
# T1 ARMv6T2, ARMv7
111110101011(Rm:4)1111(Rd:4)1000(Rm2:4)	CLZ_T1

# A8.8.34 CMN (immediate)
# T1 ARMv6T2, ARMv7
11110i010001(Rn:4)0(imm3:3)1111(imm8:8)	CMN_imm_T1

# A8.8.35 CMN (register)
# T2 ARMv6T2, ARMv7
111010110001(Rn:4)(0)(imm3:3)1111(imm2:2)(type:2)(Rm:4)	CMN_reg_T2

# A8.8.37 CMP (immediate)
# T2 ARMv6T2, ARMv7
11110i011011(Rn:4)0(imm3:3)1111(imm8:8)	CMP_imm_T2

# A8.8.38 CMP (register)
# T3 ARMv6T2, ARMv7
111010111011(Rn:4)(0)(imm3:3)1111(imm2:2)(type:2)(Rm:4)	CMP_reg_T3

# A8.8.42 DBG
# T1 ARMv7
111100111010(1111)10(0)0(0)0001111(option:4)	DBG_T1

# A8.8.43 DMB
# T1 ARMv7
111100111011(1111)10(0)0(1111)0101(option:4)	DMB_T1

# A8.8.44 DSB
# T1 ARMv7
111100111011(1111)10(0)0(1111)0100(option:4)	DSB_T1

# A8.8.46 EOR (immediate)
# T1 ARMv6T2, ARMv7
11110i00100S(Rn:4)0(imm3:3)(Rd:4)(imm8:8)	{lor(ne(Rd,15),ne(S,1))}	EOR_imm_T1

# A8.8.47 EOR (register)
# T2 ARMv6T2, ARMv7
11101010100S(Rn:4)(0)(imm3:3)(Rd:4)(imm2:2)(type:2)(Rm:4)	{lor(ne(Rd,15),ne(S,1))}	EOR_reg_T2

# A8.8.53 ISB
# T1 ARMv7
111100111011(1111)10(0)0(1111)0110(option:4)	ISB_T1

# A8.8.55 LDC, LDC2 (immediate)
# T1 ARMv6T2, ARMv7
111011000001(Rn:4)(CRd:4)(coproc:4)(imm8:8)	{ne(coproc,10)} {ne(coproc,11)} {ne(Rn,15)} [LDC_STC]	UNDEFINED
1110110PUDW1(Rn:4)(CRd:4)(coproc:4)(imm8:8)	{ne(coproc,10)} {ne(coproc,11)} {ne(Rn,15)} {lor(lor(P,U),W)} [LDC_STC]	LDC_LDC2_imm_T1
# T2 ARMv6T2, ARMv7
111111000001(Rn:4)(CRd:4)(coproc:4)(imm8:8)	{ne(Rn,15)}	UNDEFINED
1111110PUDW1(Rn:4)(CRd:4)(coproc:4)(imm8:8)	{ne(Rn,15)} {lor(lor(P,U),W)}	LDC_LDC2_imm_T2

# A8.8.56 LDC, LDC2 (literal)
# T1 ARMv6T2, ARMv7
1110110000011111(CRd:4)(coproc:4)(imm8:8)	{ne(coproc,10)} {ne(coproc,11)} [LDC_STC]	UNDEFINED
1110110PUDW11111(CRd:4)(coproc:4)(imm8:8)	{ne(coproc,10)} {ne(coproc,11)} {lor(lor(P,U),W)} [LDC_STC]	LDC_LDC2_lit_T1
# T2 ARMv6T2, ARMv7
1111110000011111(CRd:4)(coproc:4)(imm8:8)	UNDEFINED
1111110PUDW11111(CRd:4)(coproc:4)(imm8:8)	{lor(lor(P,U),W)}	LDC_LDC2_lit_T2

# A8.8.57 LDM/LDMIA/LDMFD (Thumb)
# T2 ARMv6T2, ARMv7
1110100010W1(Rn:4)PM(0)(reglist:13)	{lor(ne(W,1),ne(Rn,13))}	LDMIA_T2

# A8.8.60 LDMDB/LDMEA
# T1 ARMv6T2, ARMv7
1110100100W1(Rn:4)PM(0)(reglist:13)	LDMDB_T1

# A8.8.62 LDR (immediate, Thumb)
# T3 ARMv6T2, ARMv7
111110001101(Rn:4)(Rt:4)(imm12:12)	{ne(Rn,15)}	LDR_imm_T3
# T4 ARMv6T2, ARMv7
111110000101(Rn:4)(Rt:4)1PUW(imm8:8)	{ne(Rn,15)} {lnot(land(land(P,U),lnot(W)))} {lnot(land(land(land(eq(Rn,13),lnot(P)),land(U,W)),eq(imm8,4)))} {lor(P,W)}	LDR_imm_T4
111110000101(Rn:4)(Rt:4)1PUW(imm8:8)	{ne(Rn,15)} {lnot(land(land(P,U),lnot(W)))} {lnot(land(land(land(eq(Rn,13),lnot(P)),land(U,W)),eq(imm8,4)))} {lnot(lor(P,W))}	UNDEFINED

# A8.8.64 LDR (literal)
# T2 ARMv6T2, ARMv7
11111000U1011111(Rt:4)(imm12:12)	LDR_lit_T2

# A8.8.65 LDR (register, Thumb)
# T2 ARMv6T2, ARMv7
111110000101(Rn:4)(Rt:4)000000(imm2:2)(Rm:4)	{ne(Rn,15)}	LDR_reg_T2

# A8.8.67 LDRB (immediate, Thumb)
# T2 ARMv6T2, ARMv7
111110001001(Rn:4)(Rt:4)(imm12:12)	{ne(Rt,15)} {ne(Rn,15)}	LDRB_imm_T2
# T3 ARMv6T2, ARMv7
111110000001(Rn:4)(Rt:4)1PUW(imm8:8)	{lnot(land(land(eq(Rt,15),P),lnot(lor(U,W))))} {ne(Rn,15)} {lnot(land(land(P,U),lnot(W)))} {lor(P,W)}		LDRB_imm_T3
111110000001(Rn:4)(Rt:4)1PUW(imm8:8)	{lnot(land(land(eq(Rt,15),P),lnot(lor(U,W))))} {ne(Rn,15)} {lnot(land(land(P,U),lnot(W)))} {lnot(lor(P,W))}	UNDEFINED

# A8.8.69 LDRB (literal)
# T1 ARMv6T2, ARMv7
11111000U0011111(Rt:4)(imm12:12)	{ne(Rt,15)}	LDRB_lit_T1

# A8.8.70 LDRB (register)
# T2 ARMv6T2, ARMv7
111110000001(Rn:4)(Rt:4)000000(imm2:2)(Rm:4)	{ne(Rt,15)} {ne(Rn,15)}	LDRB_reg_T2

# A8.8.71 LDRBT
# T1 ARMv6T2, ARMv7
111110000001(Rn:4)(Rt:4)1110(imm8:8)	{ne(Rn,15)}			LDRBT_T1

# A8.8.72 LDRD (immediate)
# T1 ARMv6T2, ARMv7
1110100PU1W1(Rn:4)(Rt:4)(Rt2:4)(imm8:8)	{lor(P,W)} {ne(Rn,15)}	LDRD_imm_T1

# A8.8.73 LDRD (literal)
# T1 ARMv6T2, ARMv7
1110100PU1W11111(Rt:4)(Rt2:4)(imm8:8)	{lor(P,W)}	LDRD_lit_T1

# A8.8.75 LDREX
# T1 ARMv6T2, ARMv7
111010000101(Rn:4)(Rt:4)(1111)(imm8:8)	LDREX_T1

# A8.8.76 LDREXB
# T1 ARMv7
111010001101(Rn:4)(Rt:4)(1111)0100(1111)	LDREXB_T1

# A8.8.77 LDREXD
# T1 ARMv7
111010001101(Rn:4)(Rt:4)(Rt2:4)0111(1111)	LDREXD_T1

# A8.8.78 LDREXH
# T1 ARMv7
111010001101(Rn:4)(Rt:4)(1111)0101(1111)	LDREXH_T1

# A8.8.79 LDRH (immediate, Thumb)
# T2 ARMv6T2, ARMv7
111110001011(Rn:4)(Rt:4)(imm12:12)	{ne(Rt,15)} {ne(Rn,15)}	LDRH_imm_T1
# T3 ARMv6T2, ARMv7
111110000011(Rn:4)(Rt:4)1PUW(imm8:8)	{ne(Rn,15)} {lnot(land(land(eq(Rt,15),P),lnot(lor(U,W))))} {lnot(land(land(P,U),lnot(W)))} {lor(P,W)}	LDRH_imm_T2
111110000011(Rn:4)(Rt:4)1PUW(imm8:8)	{ne(Rn,15)} {lnot(land(land(eq(Rt,15),P),lnot(lor(U,W))))} {lnot(land(land(P,U),lnot(W)))} {lnot(lor(P,W))}	UNDEFINED

# A8.8.81 LDRH (literal)
# T1 ARMv6T2, ARMv7
11111000U0111111(Rt:4)(imm12:12)	{ne(Rt,15)}	LDRH_lit_T1

# A8.8.82 LDRH (register)
# T2 ARMv6T2, ARMv7
111110000011(Rn:4)(Rt:4)000000(imm2:2)(Rm:4)	{ne(Rn,15)} {ne(Rt,15)}	LDRH_reg_T2

# A8.8.83 LDRHT
# T1 ARMv6T2, ARMv7
111110000011(Rn:4)(Rt:4)1110(imm8:8)	{ne(Rn,15)}	LDRHT_T1

# A8.8.84 LDRSB (immediate)
# T1 ARMv6T2, ARMv7
111110011001(Rn:4)(Rt:4)(imm12:12)	{ne(Rt,15)} {ne(Rn,15)}	LDRSB_imm_T1
# T2 ARMv6T2, ARMv7
111110010001(Rn:4)(Rt:4)1PUW(imm8:8)	{lnot(land(land(eq(Rt,15),P),lnot(lor(U,W))))} {ne(Rn,15)} {lnot(land(land(P,U),lnot(W)))} {lor(P,W)}	LDRSB_imm_T2
111110010001(Rn:4)(Rt:4)1PUW(imm8:8)	{lnot(land(land(eq(Rt,15),P),lnot(lor(U,W))))} {ne(Rn,15)} {lnot(land(land(P,U),lnot(W)))} {lnot(lor(P,W))}	UNDEFINED

# A8.8.85 LDRSB (literal)
# T1 ARMv6T2, ARMv7
11111001U0011111(Rt:4)(imm12:12)	{ne(Rt,15)}	LDRSB_lit_T1

# A8.8.86 LDRSB (register)
# T2 ARMv6T2, ARMv7
111110010001(Rn:4)(Rt:4)000000(imm2:2)(Rm:4)	{ne(Rt,15)} {ne(Rn,15)}	LDRSB_reg_T2

# A8.8.87 LDRSBT
# T1 ARMv6T2, ARMv7
111110010001(Rn:4)(Rt:4)1110(imm8:8)	{ne(Rn,15)}	LDRSBT_T1

# A8.8.88 LDRSH (immediate)
# T1 ARMv6T2, ARMv7
111110011011(Rn:4)(Rt:4)(imm12:12)	{ne(Rn,15)} {ne(Rt,15)}	LDRSH_imm_T1
# T2 ARMv6T2, ARMv7
111110010011(Rn:4)(Rt:4)1PUW(imm8:8)	{ne(Rn,15)} {lnot(land(land(eq(Rt,15),P),lnot(lor(U,W))))} {lnot(land(land(P,U),lnot(W)))} {lor(P,W)}	LDRSH_imm_T2
111110010011(Rn:4)(Rt:4)1PUW(imm8:8)	{ne(Rn,15)} {lnot(land(land(eq(Rt,15),P),lnot(lor(U,W))))} {lnot(land(land(P,U),lnot(W)))} {lnot(lor(P,W))}	UNDEFINED

# A8.8.89 LDRSH (literal)
# T1 ARMv6T2, ARMv7
11111001U0111111(Rt:4)(imm12:12)	{ne(Rt,15)}	LDRSH_lit_T1

# A8.8.90 LDRSH (register)
# T1 ARMc6T2, ARMv7
111110010011(Rn:4)(Rt:4)000000(imm2:2)(Rm:4)	{ne(Rn,15)} {ne(Rt,15)}	LDRSH_reg_T1

# A8.8.91 LDRSHT
# T1 ARMv6T2, ARMv7
111110010011(Rn:4)(Rt:4)1110(imm8:8)	{ne(Rn,15)}	LDRSHT_T1

# A8.8.92 LDRT
# T1 ARMv6T2, ARMv7
111110000101(Rn:4)(Rt:4)1110(imm8:8)	{ne(Rn,15)}	LDRT_T1

# A8.8.94 LSL (immediate)
# T2 ARMv6T2, ARMv7
11101010010S1111(0)(imm3:3)(Rd:4)(imm2:2)00(Rm:4)	{lor(imm3,imm2)}	LSL_imm_T2

# A8.8.95 LSL (register)
# T2 ARMv6T2, ARMv7
11111010000S(Rn:4)1111(Rd:4)0000(Rm:4)	LSL_reg_T2

# A8.8.96 LSR (immediate)
# T2 ARMv6T2, ARMv7
11101010010S1111(0)(imm3:3)(Rd:4)(imm2:2)01(Rm:4)	LSR_imm_T2

# A8.8.97 LSR (register)
# T2 ARMv6T2, ARMv7
11111010001S(Rn:4)1111(Rd:4)0000(Rm:4)	LSR_reg_T2

# A8.8.98 MCR, MCR2
# T1 ARMv6T2, ARMv7
11101110(opc1:3)0(Crn:4)(Rt:4)(coproc:4)(opc2:3)1(CRm:4)	{ne(coproc,10)} {ne(coproc,11)} [MRC_MCR]	MCR_MCR2_T1
# T2 ARMv6T2, ARMv7
11111110(opc1:3)0(Crn:4)(Rt:4)(coproc:4)(opc2:3)1(CRm:4)	MCR_MCR2_T2

# A8.8.99 MCRR, MCRR2
# T1 ARMv6T2, ARMv7
111011000100(Rt2:4)(Rt:4)(coproc:4)(opc1:4)(CRm:4)	{ne(coproc,10)} {ne(coproc,11)} [LDC_STC]	MCRR_MCRR2_T1
# T2 ARMv6T2, ARMv7
111111000100(Rt2:4)(Rt:4)(coproc:4)(opc1:4)(CRm:4)	MCRR_MCRR2_T2

# A8.8.100 MLA
# T1 ARMv6T2, ARMv7
111110110000(Rn:4)(Ra:4)(Rd:4)0000(Rm:4)	{ne(Ra,15)}	MLA_T1

# A8.8.101 MLS
# T1 ARMv6T2, ARMv7
111110110000(Rn:4)(Ra:4)(Rd:4)0001(Rm:4)	MLS_T1

# A8.8.102 MOV (immediate)
# T2 ARMv6T2, ARMv7
11110i00010S11110(imm3:3)(Rd:4)(imm8:8)	MOV_imm_T2
# T3 ARMv6T2, ARMv7
11110i100100(imm4:4)0(imm3:3)(Rd:4)(imm8:8)	MOV_imm_T3

# A8.8.103 MOV (register, Thumb)
# T3 ARMv6T2, ARMv7
11101010010S1111(0)000(Rd:4)0000(Rm:4)	MOV_reg_T3

# A8.8.106 MOVT
# T1 ARMv6T2, ARMv7
11110i101100(imm4:4)0(imm3:3)(Rd:4)(imm8:8)	MOVT_T1

# A8.8.107 MRC, MRC2
# T1 ARMv6T2, ARMv7
11101110(opc1:3)1(CRn:4)(Rt:4)(coproc:4)(opc2:3)1(CRm:4)	{ne(coproc,10)} {ne(coproc,11)} [MRC_MCR]	MRC_MRC2_T1
# T2 ARMv6T2, ARMv7
11111110(opc1:3)1(CRn:4)(Rt:4)(coproc:4)(opc2:3)1(CRm:4)	MRC_MRC2_T2

# A8.8.108 MRRC, MRRC2
# T1 ARMv6T2, ARMv7
111011000101(Rt2:4)(Rt:4)(coproc:4)(opc1:4)(CRm:4)	{ne(coproc,10)} {ne(coproc,11)} [LDC_STC]	MRRC_MRRC2_T1
# T2 ARMv6T2, ARMv7
111111000101(Rt2:4)(Rt:4)(coproc:4)(opc1:4)(CRm:4)	MRRC_MRRC2_T2

# A8.8.109 MRS
# T1 ARMv6T2, ARMv7
#111100111110(1111)10(0)0(Rd:4)(00000000)	MRS_T1 # - covered by B6.1.5

# A8.8.112 MSR (register)
# T1 ARMv6T2, ARMv7
#111100111000(Rn:4)10(0)0(mask:2)00(00000000)	MSR_reg_T1 # - covered by B6.1.7

# A8.8.114 MUL
# T2 ARMv6T2, ARMv7
111110110000(Rn:4)1111(Rd:4)0000(Rm:4)	MUL_T2

# A8.8.115 MVN (immediate)
# T1 ARMv6T2, ARMv7
11110i00011S11110(imm3:3)(Rd:4)(imm8:8)	MVN_imm_T1

# A8.8.116 MVN (register)
# T1 ARMv6T2, ARMv7
11101010011S1111(0)(imm3:3)(Rd:4)(imm2:2)(type:2)(Rm:4)	MVN_reg_T2

# A8.8.119 NOP
# T2 ARMv6T2, ARMv7
111100111010(1111)10(0)0(0)00000000000	NOP_T2

# A8.8.120 ORN (immediate)
# T1 ARMv6T2, ARMv7
11110I00011S(Rn:4)0(imm3:3)(Rd:4)(imm8:8)	{ne(Rn,15)}	ORN_imm_T1

# A8.8.121 ORN (register)
# T1 ARMv6T2, ARMv7
11101010011S(Rn:4)(0)(imm3:3)(Rd:4)(imm2:2)(type:2)(Rm:4)	{ne(Rn,15)}	ORN_reg_T1

# A8.8.122 ORR (immediate)
# T1 ARMv6T2, ARMv7
11110i00010S(Rn:4)0(imm3:3)(Rd:4)(imm8:8)	{ne(Rn,15)}	ORR_imm_T1

# A8.8.123 ORR (register)
# T2 ARMv6T2, ARMv7
11101010010S(Rn:4)(0)(imm3:3)(Rd:4)(imm2:2)(type:2)(Rm:4)	{ne(Rn,15)}	ORR_reg_T2

# A8.8.125 PKH
# T1 ARMv6T2, ARMv7
11101010110S(Rn:4)(0)(imm3:3)(Rd:4)(imm2:2)(tb)T(Rm:4)	PKH_T1
11101010110S(Rn:4)(0)(imm3:3)(Rd:4)(imm2:2)(tb)T(Rm:4)	{lor(S,T)}	UNDEFINED in PKH_T1

# A8.8.126 PLD, PLDW (immediate)
# T1 ARMv6T2, ARMv7
1111100010W1(Rn:4)1111(imm12:12)	{ne(Rn,15)} {lnot(W)}	PLD_imm_T1a
# T1 ARMv7MP
1111100010W1(Rn:4)1111(imm12:12)	{ne(Rn,15)} {W}		PLD_imm_T1b
# T2 ARMv6T2, ARMv7
1111100000W1(Rn:4)11111100(imm8:8)	{ne(Rn,15)} {lnot(W)}	PLD_imm_T2a
# T2 ARMv7MP
1111100000W1(Rn:4)11111100(imm8:8)	{ne(Rn,15)} {W}	PLD_imm_T2a

# A8.8.127 PLD (literal)
# T1 ARMv6T2, ARMv7
11111000U0(0)111111111(imm12:12)	PLD_lit_T1

# A8.8.128 PLD, PLDW (register)
# T1 ARMv6T2, ARMv7
1111100000W1(Rn:4)1111000000(imm2:2)(Rm:4)	{ne(Rn,15)} {lnot(W)}	PLD_reg_T1a
# T1 ARMv7MP
1111100000W1(Rn:4)1111000000(imm2:2)(Rm:4)	{ne(Rn,15)} {W}	PLD_reg_T1b

# A8.8.129 PLI (immediate, literal)
# T1 ARMv7
111110011001(Rn:4)1111(imm12:12)	{ne(Rn,15)}	PLI_imm_lit_T1
# T2 ARMv7
111110010001(Rn:4)11111100(imm8:8)	{ne(Rn,15)}	PLI_imm_lit_T2
# T3 ARMv7
11111001U00111111111(imm12:12)	PLI_imm_lit_T3

# A8.8.130 PLI (register)
# T1 ARMv7
111110010001(Rn:4)1111000000(imm2:2)(Rm:4)	{ne(Rn,15)}	PLI_reg_T1

# A8.8.131 POP (Thumb)
# T2 ARMv6T2, ARMv7
1110100010111101PM(0)(reglist:13)	POP_T2
# T3 ARMv6T2, ARMv7
1111100001011101(Rt:4)101100000100	POP_T3

# A8.8.133 PUSH
# T2 ARMv6T2, ARMv7
1110100100101101(0)M(0)(reglist:13)	PUSH_T2
# T3 ARMv6T2, ARMv7
1111100001001101(Rt:4)110100000100	PUSH_T3

# A8.8.134 QADD
# T1 ARMv6T2, ARMv7
111110101000(Rn:4)1111(Rd:4)1000(Rm:4)	QADD_T1

# A8.8.135 QADD16
# T1 ARMv6T2, ARMv7
111110101001(Rn:4)1111(Rd:4)0001(Rm:4)	QADD16_T1

# A8.8.136 QADD8
# T1 ARMv6T2, ARMv7
111110101000(Rn:4)1111(Rd:4)0001(Rm:4)	QADD8_T1

# A8.8.137 QASX
# T1 ARMv6T2, ARMv7
111110101010(Rn:4)1111(Rd:4)0001(Rm:4)	QASX_T1

# A8.8.138 QDADD
# T1 ARMv6T2, ARMv7
111110101000(Rn:4)1111(Rd:4)1001(Rm:4)	QDADD_T1

# A8.8.139 QDSUB
# T1 ARMv6T2, ARMv7
111110101000(Rn:4)1111(Rd:4)1011(Rm:4)	QDSUB_T1

# A8.8.140 QSAX
# T1 ARMv6T2, ARMv7
111110101110(Rn:4)1111(Rd:4)0001(Rm:4)	QSAX_T1

# A8.8.141 QSUB
# T1 ARMv6T2, ARMv7
111110101000(Rn:4)1111(Rd:4)1010(Rm:4)	QSUB_T1

# A8.8.142 QSUB16
# T1 ARMv6T2, ARMv7
111110101101(Rn:4)1111(Rd:4)0001(Rm:4)	QSUB16_T1

# A8.8.143 QSUB8
# T1 ARMv6T2, ARMv7
111110101100(Rn:4)1111(Rd:4)0001(Rm:4)	QSUB8_T1

# A8.8.144 RBIT
# T1 ARMv6T2, ARMv7
111110101001(Rm:4)1111(Rd:4)1010(Rm2:4)	RBIT_T1

# A8.8.145 REV
# T2 ARMv6T2, ARMv7
111110101001(Rm:4)1111(Rd:4)1000(Rm2:4)	REV_T2

# A8.8.148 REV16
# T2 ARMv6T2, ARMv7
111110101001(Rm:4)1111(Rd:4)1001(Rm2:4)	REV16_T2

# A8.8.147 REVSH
# T2 ARMv6T2, ARMv7
111110101001(Rm:4)1111(Rd:4)1011(Rm2:4)	REVSH_T2

# A8.8.149 ROR (immediate)
# T1 ARMv6T2, ARMv7
11101010010S1111(0)(imm3:3)(Rd:4)(imm2:2)11(Rm:4)	{lor(imm3,imm2)}	ROR_imm_T1

# A8.8.150 ROR (register)
# T2 ARMv6T2, ARMv7
11111010011S(Rn:4)1111(Rd:4)0000(Rm:4)	ROR_reg_T2

# A8.8.151 RRX
# T1 ARMv6T2, ARMv7
11101010010S1111(0)000(Rd:4)0011(Rm:4)	RRX_T1

# A8.8.152 RSB (immediate)
# T2 ARMv6T2, ARMv7
11110i01110S(Rn:4)0(imm3:3)(Rd:4)(imm8:8)	RSB_imm_T2

# A8.8.153 RSB (register)
# T1 ARMv6T2, ARMv7
11101011110S(Rn:4)(0)(imm3:3)(Rd:4)(imm2:2)(type:2)(Rm:4)	RSB_reg_T1

# A8.8.158 SADD16
# T1 ARMv6T2, ARMv7
111110101001(Rn:4)1111(Rd:4)0000(Rm:4)	SADD16_T1

# A8.8.159 SADD8
# T1 ARMv6T2, ARMv7
111110101000(Rn:4)1111(Rd:4)0000(Rm:4)	SADD8_T1

# A8.8.160 SASX
# T1 ARMv6T2, ARMv7
111110101010(Rn:4)1111(Rd:4)0000(Rm:4)	SASX_T1

# A8.8.161 SBC (immediate)
# T1 ARMv6T2, ARMv7
11110i01011S(Rn:4)0(imm3:3)(Rd:4)(imm8:8)	SBC_imm_T1

# A8.8.162 SBC (register)
# T2 ARMv6T2, ARMv7
11101011011s(Rn:4)(0)(imm3:3)(Rd:4)(imm2:2)(type:2)(Rm:4)	SBC_reg_T2

# A8.8.164 SBFX
# T1 ARMv6T2, ARMv7
11110(0)110100(Rn:4)0(imm3:3)(Rd:4)(imm2:2)(0)(widthm1:5)	SBFX_T1

# A8.8.165 SDIV
# T1 ARMv7-R, ARMv7VE, ARMv7opt
111110111001(Rn:4)(1111)(Rd:4)1111(Rm:4)	SDIV_T1

# A8.8.166 SEL
# T1 ARMv6T2, ARMv7
111110101010(Rn:4)1111(Rd:4)1000(Rm:4)	SEL_T1

# A8.8.168 SEV
# T2 ARMv7
111100111010(1111)10(0)0(0)00000000100	SEV_T2

# A8.8.169 SHADD16
# T1 ARMv6T2, ARMv7
111110101001(Rn:4)1111(Rd:4)0010(Rm:4)	SHADD16_T1

# A8.8.170 SHADD8
# T1 ARMv6T2, ARMv7
111110101000(Rn:4)1111(Rd:4)0010(Rm:4)	SHADD8_T1

# A8.8.171 SHASX
# T1 ARMv6T2, ARMv7
111110101010(Rn:4)1111(Rd:4)0010(Rm:4)	SHASX_T1

# A8.8.172 SHSAX
# T1 ARMv6T2, ARMv7
111110101110(Rn:4)1111(Rd:4)0010(Rm:4)	SHSAX_T1

# A8.8.173 SHSUB16
# T1 ARMv6T2, ARMv7
111110101101(Rn:4)1111(Rd:4)0010(Rm:4)	SHSUB16_T1

# A8.8.174 SHSUB8
# T1 ARMv6T2, ARMv7
111110101100(Rn:4)1111(Rd:4)0010(Rm:4)	SHSUB8_T1

# A8.8.176 SMLABB, SMLABT, SMLATB, SMLATT
# T1 ARMv6T2, ARMv7
111110110001(Rn:4)(Ra:4)(Rd:4)00NM(Rm:4)	{ne(Ra,15)}	SMLAxx_T1

# A8.8.177 SMLAD
# T1 ARMv6T2, ARMv7
111110110010(Rn:4)(Ra:4)(Rd:4)000M(Rm:4)	{ne(Ra,15)}	SMLAD_T1

# A8.8.178 SMLAL
# T1 ARMv6T2, ARMv7
111110111100(Rn:4)(RdLo:4)(RdHi:4)0000(Rm:4)	SMLAL_T1

# A8.8.179 SMLALBB, SMLALBT, SMLALTB, SMLALTT
# T1 ARMv6T2, ARMv7
111110111100(Rn:4)(RdLo:4)(Rdhi:4)10NM(Rm:4)	SMLALxx_T1

# A8.8.180 SMLALD
# T1 ARMv6T2, ARMv7
111110111100(Rn:4)(RdLo:4)(RdHi:4)110M(Rm:4)	SMLALD_T1

# A8.8.181 SMLAWB, SMLAWT
# T1 ARMv6T2, ARMv7
111110110011(Rn:4)(Ra:4)(Rd:4)000M(Rm:4)	{ne(Ra,15)}	SMLAWx_T1

# A8.8.182 SMLSD
# T1 ARMv6T2, ARMv7
111110110100(Rn:4)(Ra:4)(Rd:4)000M(Rm:4)	{ne(Ra,15)}	SMLSD_T1

# A8.8.183 SMLSLD
# T1 ARMv6T2, ARMv7
111110111101(Rn:4)(RdLo:4)(RdHi:4)110M(Rm:4)	SMLSLD_T1

# A8.8.184 SMMLA
# T1 ARMv6T2, ARMv7
111110110101(Rn:4)(Ra:4)(Rd:4)000R(Rm:4)	{ne(Ra,15)}	SMMLA_T1

# A8.8.185 SMMLS
# T1 ARMv6T2, ARMv7
111110110110(Rn:4)(Ra:4)(Rd:4)000R(Rm:4)	SMMLS_T1

# A8.8.186 SMMUL
# T1 ARMv6T2, ARMv7
111110110101(Rn:4)1111(Rd:4)000R(Rm:4)	SMMUL_T1

# A8.8.187 SMUAD
# T1 ARMv6T2, ARMv7
111110110010(Rn:4)1111(Rd:4)000M(Rm:4)	SMUAD_T1

# A8.8.188 SMULBB, SMULBT, SMULTB, SMULTT
# T1 ARMv6T2, ARMv7
111110110001(Rn:4)1111(Rd:4)00NM(Rm:4)	SMULxx_T1

# A8.8.189 SMULL
# T1 ARMv6T2, ARMv7
111110111000(Rn:4)(RdLo:4)(RdHi:4)0000(Rm:4)	SMULL_T1

# A8.8.190 SMULWB, SMULWT
# T1 ARMv6T2, ARMv7
111110110011(Rn:4)1111(Rd:4)000M(Rm:4)	SMULWx_T1

# A8.8.191 SMUSD
# T1 ARMv6T2, ARMv7
111110110100(Rn:4)1111(Rd:4)000M(Rm:4)	SMUSD_T1

# A8.8.193 SSAT
# T1 ARMv6T2, ARMv7
11110(0)1100(sh)0(Rn:4)0(imm3:3)(Rd:4)(imm2:2)(0)(sat_imm:5)	{lor(lnot(sh),lor(imm3,imm2))}	SSAT_T1

# A8.8.194 SSAT16
# T1 ARMv6T2, ARMv7
11110(0)110010(Rn:4)0000(Rd:4)00(00)(sat_imm:4)	SSAT16_T1

# A8.8.195 SSAX
# T1 ARMv6T2, ARMv7
111110101110(Rn:4)1111(Rd:4)0000(Rm:4)	SSAX_T1

# A8.8.196 SSUB16
# T1 ARMv6T2, ARMv7
111110101101(Rn:4)1111(Rd:4)0000(Rm:4)	SSUB16_T1

# A8.8.197 SSUB8
# T1 ARMv6T2, ARMv7
111110101100(Rn:4)1111(Rd:4)0000(Rm:4)	SSUB8_T1

# A8.8.198 STC, STC2
# T1 ARMv6T2, ARMv7
111011000000(Rn:4)(CRd:4)(coproc:4)(imm8:8)	{ne(coproc,10)} {ne(coproc,11)} [LDC_STC]	UNDEFINED
1110110PUDW0(Rn:4)(CRd:4)(coproc:4)(imm8:8)	{lor(lor(P,U),W)} {ne(coproc,10)} {ne(coproc,11)} [LDC_STC]	STC_STC2_T1
# T2 ARMv6T2, ARMv7
111111000000(Rn:4)(CRd:4)(coporc:4)(imm8:8)	UNDEFINED
1111110PUDW0(Rn:4)(CRd:4)(coporc:4)(imm8:8)	{lor(lor(P,U),W)}	STC_STC2_T2

# A8.8.199 STM/STMIA/STMEA
# T2 ARMv6T2, ARMv7
1110100010W0(Rn:4)(0)M(0)(reglist:13)	STMIA_T2

# A8.8.201 STMDB/STMFD
# T1 ARMv6T2, ARMv7
1110100100W0(Rn:4)(0)M(0)(reglist:13)	{lnot(land(W,eq(Rn,13)))}	STMDB_T1

# A8.8.203 STR (immediate, Thumb)
# T3 ARMv6T2, ARMv7
111110001100(Rn:4)(Rt:4)(imm12:12)	{ne(Rn,15)}	STR_imm_T3
1111100011001111(Rt:4)(imm12:12)	UNDEFINED
# T4 ARMv6T2, ARMv7
111110000100(Rn:4)(Rt:4)1PUW(imm8:8)	{lor(lnot(land(P,U)),W)} {lnot(land(land(land(eq(Rn,13),P),land(lnot(U),W)),eq(imm8,4)))} {ne(Rn,15)} {lor(P,W)}	STR_imm_T4
111110000100(Rn:4)(Rt:4)1PUW(imm8:8)	{lor(lnot(land(P,U)),W)} {lnot(land(land(land(eq(Rn,13),P),land(lnot(U),W)),eq(imm8,4)))} {lor(eq(Rn,15),lnot(lor(P,W)))}	UNDEFINED

# A8.8.205 STR (register)
# T2 ARMv6T2, ARMv7
111110000100(Rn:4)(Rt:4)000000(imm2:2)(Rm:4)	{ne(Rn,15)}	STR_reg_T2
1111100001001111(Rt:4)000000(imm2:2)(Rm:4)	UNDEFINED

# A8.8.206 STRB (immediate, Thumb)
# T2 ARMv6T2, ARMv7
111110001000(Rn:4)(Rt:4)(imm12:12)	{ne(Rn,15)}	STRB_imm_T2
1111100010001111(Rt:4)(imm12:12)	UNDEFINED
# T3 ARMv6T2, ARMv7
111110000000(Rn:4)(Rt:4)1PUW(imm8:8)	{lor(lnot(land(P,U)),W)} {ne(Rn,15)} {lor(P,W)}	STRB_imm_T3
111110000000(Rn:4)(Rt:4)1PUW(imm8:8)	{lor(lnot(land(P,U)),W)} {lor(eq(Rn,15),lnot(lor(P,W)))}	UNDEFINED

# A8.8.208 STRB (register)
# T2 ARMv6T2, ARMv7
111110000000(Rn:4)(Rt:4)000000(imm2:2)(Rm:4)	{ne(Rn,15)}	STRB_reg_T2
1111100000001111(Rt:4)000000(imm2:2)(Rm:4)	UNDEFINED

# A8.8.209 STRBT
# T1 ARMv6T2, ARMv7
111110000000(Rn:4)(Rt:4)1110(imm8:8)	{ne(Rn,15)}	STRBT_T1
1111100000001111(Rt:4)1110(imm8:8)	UNDEFINED

# A8.8.210 STRD (immediate)
# T1 ARMv6T2, ARMv7
1110100PU1W0(Rn:4)(Rt:4)(Rt2:4)(imm8:8)	{lor(P,W)}	STRD_imm_T1

# A8.8.212 STREX
# T1 ARMv6T2, ARMv7
111010000100(Rn:4)(Rt:4)(Rd:4)(imm8:8)	STREX_T1

# A8.8.213 STREXB
# T1 ARMv7
111010001100(Rn:4)(Rt:4)(1111)0100(Rd:4)	STREXB_T1

# A8.8.214 STREXD
# T1 ARMv7
111010001100(Rn:4)(Rt:4)(Rt2:4)0111(Rd:4)	STREXD_T1

# A8.8.215 STREXH
# T1 ARMv7
111010001100(Rn:4)(Rt:4)(1111)0101(Rd:4)	STREXH_T1

# A8.8.216 STRH (immediate, Thumb)
# T2 ARMv6T2, ARMv7
111110001010(Rn:4)(Rt:4)(imm12:12)	{ne(Rn,15)}	STRH_imm_T2
1111100010101111(Rt:4)(imm12:12)	UNDEFINED
# T3 ARMv6T2, ARMv7
111110000010(Rn:4)(Rt:4)1PUW(imm8:8)	{lor(lnot(land(P,U)),W)} {ne(Rn,15)} {lor(P,W)}	STR_imm_T3
111110000010(Rn:4)(Rt:4)1PUW(imm8:8)	{lor(lnot(land(P,U)),W)} {lor(eq(Rn,15),lnot(lor(P,W)))}	UNDEFINED

# A8.8.218 STRH (register)
# T2 ARMv6T2, ARMv7
111110000010(Rn:4)(Rt:4)000000(imm2:2)(Rm:4)	{ne(Rn,15)}	STRH_reg_T2
1111100000101111(Rt:4)000000(imm2:2)(Rm:4)	UNDEFINED

# A8.8.219 STRHT
# T1 ARMv6T2, ARMv7
111110000010(Rn:4)(Rt:4)1110(imm8:8)	{ne(Rn,15)}	STRHT_T1
1111100000101111(Rt:4)1110(imm8:8)	UNDEFINED

# A8.8.220 STRT
# T1 ARMv6T2, ARMv7
111110000100(Rn:4)(Rt:4)1110(imm8:8)	{ne(Rn,15)}	STRT_T1
1111100001001111(Rt:4)1110(imm8:8)	UNDEFINED

# A8.8.221 SUB (immediate, Thumb)
# T3 ARMv6T2, ARMv7
11110i01101S(Rn:4)0(imm3:3)(Rd:4)(imm8:8)	{lor(ne(Rd,15),lnot(S))} {ne(Rn,13)}	SUB_imm_T3
# T4 ARMv6T2, ARMv7
11110i101010(Rn:4)0(imm3:3)(Rd:4)(imm8:8)	{ne(Rn,15)} {ne(Rn,13)}	SUB_imm_T4

# A8.8.223 SUB (register)
# T2 ARMv6T2, ARMv7
11101011101S(Rn:4)(0)(imm3:3)(Rd:4)(imm2:2)(type:2)(Rm:4)	{lor(ne(Rd,15),lnot(S))} {ne(Rn,13)}	SUB_reg_T2

# A8.8.225 SUB (SP minus immediate)
# T2 ARMv6T2, ARMv7
11110i01101S11010(imm3:3)(Rd:4)(imm8:8)	{lor(ne(Rd,15),lnot(S))}	SUB_sp_imm_T2
# T3 ARMv6T2, ARMv7
11110i10101011010(imm3:3)(Rd:4)(imm8:8)	SUB_sp_imm_T3

# A8.8.226 SUB (SP minus register)
# T1 ARMv6T2, ARMv7
11101011101S1101(0)(imm3:3)(Rd:4)(imm2:2)(type:2)(Rm:4)	{lnot(land(S,eq(Rd,15)))}	SUB_sp_reg_T1

# A8.8.230 SXTAB
# T1 ARMv6T2, ARMv7
111110100100(Rn:4)1111(Rd:4)1(0)(rotate:2)(Rm:4)	{ne(Rn,15)}	SXTAB_T1

# A8.8.231 SXTAB16
# T1 ARMv6T2, ARMv7
111110100010(Rn:4)1111(Rd:4)1(0)(rotate:2)(Rm:4)	{ne(Rn,15)}	SXTAB16_T1

# A8.8.232 SXTAH
# T1 ARMv6T2, ARMv7
111110100000(Rn:4)1111(Rd:4)1(0)(rotate:2)(Rm:4)	{ne(Rn,15)}	SXTAH_T1

# A8.8.233 SXTB
# T2 ARMv6T2, ARMv7
11111010010011111111(Rd:4)1(0)(rotate:2)(Rm:4)	SXTB_T2

# A8.8.234 SXTB16
# T1 ARMv6T2, ARMv7
11111010001011111111(Rd:4)1(0)(rotate:2)(Rm:4)	SXTB16_T1

# A8.8.235 SXTH
# T2 ARMv6T2, ARMv7
11111010000011111111(Rd:4)1(0)(rotate:2)(Rm:4)	SXTH_T2

# A8.8.238 TBB, TBH
# T1 ARMv6T2, ARMv7
111010001101(Rn:4)(11110000)000H(Rm:4)	TBB_TBH_T1

# A8.8.237 TEQ (immediate)
# T1 ARMv6T2, ARMv7
11110i001001(Rn:4)0(imm3:3)1111(imm8:8)	TEQ_imm_T1

# A8.8.238 TEQ (register)
# T1 ARMv6T2, ARMv7
111010101001(Rn:4)(0)(imm3:3)1111(imm2:2)(type:2)(Rm:4)	TEQ_reg_T1

# A8.8.240 TST (immediate)
# T1 ARMv6T2, ARMv7
11110i000001(Rn:4)0(imm3:3)1111(imm8:8)	TST_imm_T1

# A8.8.241 TST (register)
# T2 ARMv6T2, ARMv7
111010100001(Rn:4)(0)(imm3:3)1111(imm2:2)(type:2)(Rm:4)	TST_reg_T2

# A8.8.243 UADD16
# T1 ARMv6T2, ARMv7
111110101001(Rn:4)1111(Rd:4)0100(Rm:4)	UADD16_T1

# A8.8.244 UADD8
# T1 ARMv6T2, ARMv7
111110101000(Rn:4)1111(Rd:4)0100(Rm:4)	UADD8_T1

# A8.8.245 UASX
# T1 ARMv6T2, ARMv7
111110101010(Rn:4)1111(Rd:4)0100(Rm:4)	UASX_T1

# A8.8.246 UBFX
# T1 ARMv6T2, ARMv7
11110(0)111100(Rn:4)0(imm3:3)(Rd:4)(imm2:2)(0)(widthm1:5)	UBFX_T1

# A8.8.247 UDF
# T2 ARMv6T2, ARMv7
111101111111(imm4:4)1010(imm12:12)	UDF_T2

# A8.8.248 UDIV
# T1 ARMv7-R, ARMv7VE, ARMv7opt
111110111011(Rn:4)(1111)(Rd:4)1111(Rm:4)	UDIV_T1

# A8.8.249 UHADD16
# T1 ARMv6T2, ARMv7
111110101001(Rn:4)1111(Rd:4)0110(Rm:4)	UHADD16_T1

# A8.8.250 UHADD8
# T1 ARMv6T2, ARMv7
111110101000(Rn:4)1111(Rd:4)0110(Rm:4)	UHADD8_T1

# A8.8.251 UHASX
# T1 ARMv6T2, ARMv7
111110101010(Rn:4)1111(Rd:4)0110(Rm:4)	UHASX_T1

# A8.8.252 UHSAX
# T1 ARMv6T2, ARMv7
111110101110(Rn:4)1111(Rd:4)0110(Rm:4)	UHSAX_T1

# A8.8.253 UHSUB16
# T1 ARMv6T2, ARMv7
111110101101(Rn:4)1111(Rd:4)0110(Rm:4)	UHSUB16_T1

# A8.8.254 UHSUB8
# T1 ARMv6T2, ARMv7
111110101100(Rn:4)1111(Rd:4)0110(Rm:4)	UHSUB8_T1

# A8.8.255 UMAAL
# T1 ARMv6T2, ARMv7
111110111110(Rn:4)(RdLo:4)(RdHi:4)0110(Rm:4)	UMAAL_T1

# A8.8.256 UMLAL
# T1 ARMv6T2, ARMv7
111110111110(Rn:4)(RdLo:4)(RdHi:4)0000(Rm:4)	UMLAL_T1

# A8.8.257 UMULL
# T1 ARMv6T2, ARMv7
111110111010(Rn:4)(RdLo:4)(RdHi:4)0000(Rm:4)	UMULL_T1

# A8.8.258 UQADD16
# T1 ARMv6T2, ARMv7
111110101001(Rn:4)1111(Rd:4)0101(Rm:4)	UQADD16_T1

# A8.8.259 UQADD8
# T1 ARMv6T2, ARMv7
111110101000(Rn:4)1111(Rd:4)0101(Rm:4)	UQADD8_T1

# A8.8.260 UQASX
# T1 ARMv6T2, ARMv7
111110101010(Rn:4)1111(Rd:4)0101(Rm:4)	UQASX_T1

# A8.8.261 UQSAX
# T1 ARMv6T2, ARMv7
111110101110(Rn:4)1111(Rd:4)0101(Rm:4)	UQSAX_T1

# A8.8.262 UQSUB16
# T1 ARMv6T2, ARMv7
111110101101(Rn:4)1111(Rd:4)0101(Rm:4)	UQSUB16_T1

# A8.8.263 UQSUB8
# T1 ARMv6T2, ARMv7
111110101100(Rn:4)1111(Rd:4)0101(Rm:4)	UQSUB8_T1

# A8.8.264 USAD8
# T1 ARMv6T2, ARMv7
111110110111(Rn:4)1111(Rd:4)0000(Rm:4)	USAD8_T1

# A8.8.265 USADA8
# T1 ARMv6T2, ARMv7
111110110111(Rn:4)(Ra:4)(Rd:4)0000(Rm:4)	{ne(Ra,15)}	USADA8_T1

# A8.8.266 USAT
# T1 ARMv6T2, ARMv7
11110(0)1110(sh)0(Rn:4)0(imm3:3)(Rd:4)(imm2:2)(0)(sat_imm:5)	{lor(lnot(sh),lor(imm3,imm2))}	USAT_T1

# A8.8.267 USAT16
# T1 ARMv6T2, ARMv7
11110(0)111010(Rn:4)0000(Rd:4)00(00)(sat_imm:4)	USAT16_T1

# A8.8.268 USAX
# T1 ARMv6T2, ARMv7
111110101110(Rn:4)1111(Rd:4)0100(Rm:4)	USAX_T1

# A8.8.269 USUB16
# T1 ARMv6T2, ARMv7
111110101101(Rn:4)1111(Rd:4)0100(Rm:4)	USUB16_T1

# A8.8.270 USUB8
# T1 ARMv6T2, ARMv7
111110101100(Rn:4)1111(Rd:4)0100(Rm:4)	USUB8_T1

# A8.8.271 UXTAB
# T1 ARMv6T2, ARMv7
111110100101(Rn:4)1111(Rd:4)1(0)(rotate:2)(Rm:4)	{ne(Rn,15)}	UXTAB_T1

# A8.8.272 UXTAB16
# T1 ARMv6T2, ARMv7
111110100011(Rn:4)1111(Rd:4)1(0)(rotate:2)(Rm:4)	{ne(Rn,15)}	UXTAB16_T1

# A8.8.273 UXTAH
# T1 ARMv6T2, ARMv7
111110100001(Rn:4)1111(Rd:4)1(0)(rotate:2)(Rm:4)	{ne(Rn,15)}	UXTAH_T1

# A8.8.274 UXTB
# T2 ARMv6T2, ARMv7
11111010010111111111(Rd:4)1(0)(rotate:2)(Rm:4)	UXTB_T2

# A8.8.275 UXTB16
# T1 ARMv6T2, ARMv7
11111010001111111111(Rd:4)1(0)(rotate:2)(Rm:4)	UXTB16_T1

# A8.8.276 UXTH
# T2 ARMv6T2, ARMv7
11111010000111111111(Rd:4)1(0)(rotate:2)(Rm:4)	UXTH_T1

# A8.8.424 WFE
# T2 ARMv7
111100111010(1111)10(0)0(0)00000000010	WFE_T2

# A8.8.425 WFI
# T2 ARMv7
111100111010(1111)10(0)0(0)00000000011	WFI_T2

# A8.8.426 YIELD
# T2 ARMv7
111100111010(1111)10(0)0(0)00000000001	YIELD_T2

# A9.3.1 ENTERX, LEAVEX
# T1 ThumbEE
111100111011(1111)10(0)0(1111)000J(1111)	ENTERX_LEAVEX_T1

# B9.3.1 CPS (Thumb)
# T2 ARMv6T2, ARMv7
111100111010(1111)10(0)0(0)(imod:2)MAIF(mode:5)	{lor(imod,M)}	CPS_T2

# B9.3.3 ERET
# T1 ARMv6T2, ARMv7 (as SUBS PC, LR, #0), ARMv7VE (as ERET)
111100111101(1110)10(0)0(1111)(imm8:8)	{lnot(imm8)}	ERET_T1

# B9.3.4 HVC
# T1 ARMv7VE
111101111110(imm4:4)1000(imm12:12)	HVC_T1

# B9.3.8 MRS (Banked register)
# T1 ARMv7VE
11110011111R(m1:4)10(0)0(Rd:4)(00)1m(0000)	MRS_banked_T1

# B9.3.9 MRS
# T1 ARMv6T2, ARMv7
11110011111R(1111)10(0)0(Rd:4)(00)0(00000)	MRS_T1

# B9.3.10 MSR (Banked register)
# T1 ARMv7VE
11110011100R(Rn:4)10(0)0(m1:4)(00)1m(0000)	MSR_banked_T1

# B9.3.12 MSR (register)
# T1 ARMv6T2, ARMv7
11110011100R(Rn:4)10(0)0(mask:4)(00)0(00000)	MSR_reg_T1

# B9.3.13 RFE
# T1 ARMv6T2, ARMv7
1110100000W1(Rn:4)(1100000000000000)	RFE_T1
# T2 ARMv6T2, ARMv7
1110100110W1(Rn:4)(1100000000000000)	RFE_T2

# B9.3.14 SMC (previously SMI)
# T1 SecExt
111101111111(imm4:4)1000(000000000000)	SMC_T1

# B9.3.16 SRS
# T1 ARMv6T2, ARMv7
1110100000W0(110111000000000)(mode:5)	SRS_T1
# T2 ARMv6T2, ARMv7
1110100110W0(110111000000000)(mode:5)	SRS_T2

# B9.3.19 SUBS PC, LR (Thumb)
# T1 ARMv6T2, ARMv7
111100111101(1110)10(0)0(1111)(imm8:8)	{imm8}	SUBS_PC_LR_T1
