# From ARM7500FE datasheet
# Requires ARMv3/ARMv7 encoding file to be processed with:
#  CDP={ne(coproc,1)}
#  LDC_STC={ne(coproc,1)}{ne(coproc,2)}
#  MRC_MCR={ne(coproc,1)}
# Use CC to restrict NV code (i.e. -DCC= for no restriction, -DCC={ne(cond,15)} for ARM restriction, -DCC={eq(cond,14)} for Thumb2 restriction)

# 10.1.1 LDF/STF
(cond:4)110P(UD)(T1)(Wb)(LS)(Rn:4)(T0)(Fd:3)0001(offset:8)	[CC] {lor(P,Wb)}	LDF_STF
(cond:4)110P(UD)(T1)(Wb)(LS)(Rn:4)(T0)(Fd:3)0001(offset:8)	[CC] {lnot(lor(P,Wb))}	UNDEFINED

# 10.1.3 LFM/SFM
(cond:4)110P(UD)(N1)(Wb)(LS)(Rn:4)(N0)(Fd:3)0010(offset:8)	[CC] {lor(P,Wb)}	LFM_SFM
(cond:4)110P(UD)(N1)(Wb)(LS)(Rn:4)(N0)(Fd:3)0010(offset:8)	[CC] {lnot(lor(P,Wb))}	UNDEFINED

# 10.2 Floating-Point Coprocessor Data Operations
(cond:4)1110(abcd:4)1(Fn:3)(j)(Fd:3)00011(gh:2)0(i)(Fm:3)	[CC]	UNDEFINED
(cond:4)11100000(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	ADF
(cond:4)11100001(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	MUF
(cond:4)11100010(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	SUF
(cond:4)11100011(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	RSF
(cond:4)11100100(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	DVF
(cond:4)11100101(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	RDF
(cond:4)11100110(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	POW
(cond:4)11100111(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	RPW
(cond:4)11101000(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	RMF
(cond:4)11101001(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	FML
(cond:4)11101010(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	FDV
(cond:4)11101011(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	FRD
(cond:4)11101100(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	POL
(cond:4)1110(abcd:4)(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))} {gt(abcd,12)}	UNDEFINED
(cond:4)11100000(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	MVF
(cond:4)11100001(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	MNF
(cond:4)11100010(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	ABS
(cond:4)11100011(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	RND
(cond:4)11100100(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	SQT
(cond:4)11100101(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	LOG
(cond:4)11100110(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	LGN
(cond:4)11100111(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	EXP
(cond:4)11101000(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	SIN
(cond:4)11101001(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	COS
(cond:4)11101010(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	TAN
(cond:4)11101011(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	ASN
(cond:4)11101100(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	ACS
(cond:4)11101101(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	ATN
(cond:4)11101110(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	URD
(cond:4)11101111(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3)	[CC] {lnot(land(e,f))}	NRM

# 10.3 Floating-Point Coprocessor Register Transfer
(cond:4)11100000(e)(Fn:3)(Rd:4)0001(f)(gh:2)1(0)(000)	[CC] {lnot(land(e,f))}	FLT
(cond:4)11100000(e)(Fn:3)(Rd:4)0001(f)(gh:2)1(0)(000)	[CC] {land(e,f)}	UNDEFINED
(cond:4)11100001(0)(000)(Rd:4)0001(0)(gh:2)1(0)(Fm:3)	[CC]	FIX
(cond:4)11100010(0)(000)(Rd:4)0001(0)(00)1(0)(000)	[CC]	WFS
(cond:4)11100011(0)(000)(Rd:4)0001(0)(00)1(0)(000)	[CC]	RFS
(cond:4)11100100(0)(000)(Rd:4)0001(0)(00)1(0)(000)	[CC]	WFC
(cond:4)11100101(0)(000)(Rd:4)0001(0)(00)1(0)(000)	[CC]	RFC
(cond:4)1110011(LS)(0)(Fn:3)(Rd:4)0001(0)(00)1(i)(Fm:3)	[CC]	UNDEFINED
(cond:4)11101(bc:2)0(0)(Fn:3)(Rd:4)0001(0)(00)1(i)(Fm:3)	[CC]	UNDEFINED

# 10.3.1 Compare operations
(cond:4)11101001(0)(Fn:3)11110001(000)1(i)(Fm:3)	[CC]	CMF
(cond:4)11101011(0)(Fn:3)11110001(000)1(i)(Fm:3)	[CC]	CNF
(cond:4)11101101(0)(Fn:3)11110001(000)1(i)(Fm:3)	[CC]	CMFE
(cond:4)11101111(0)(Fn:3)11110001(000)1(i)(Fm:3)	[CC]	CNFE

# Undefined
(cond:4)11101(cd:2)1(e)(Fn:3)(Rd:4)0001(fgh:3)1(i)(Fm:3)	[CC] {ne(Rd,15)}	UNDEFINED # Compare with Rd!=15
