# When building with FPA support, use:
#  CDP={ne(coproc,1)}
#  LDC_STC={ne(coproc,1)}{ne(coproc,2)}
#  MRC_MCR={ne(coproc,1)}
# When building without FPA, just set the above to null

# A5.2.5
(cond:4)0000(op:4)(:12)1001(:4)	{ne(cond,15)} {lor(eq(op,5),eq(op,7))}	UNDEFINED

# A5.2.9
(cond:4)0000(:2)1(op)(:4)(Rt:4)(:4)1(op2:2)1(:4)	{ne(cond,15)} {band(op2,2)} {lnot(op)} {lnot(band(Rt,1))}	UNPREDICTABLE
(cond:4)0000(:2)1(op)(:4)(Rt:4)(:4)1(op2:2)1(:4)	{ne(cond,15)} {band(op2,2)} {lnot(op)} {band(Rt,1)}	UNDEFINED

# A5.2.10
(cond:4)0001(op:4)(:12)1001(:4)	{ne(cond,15)} {lt(op,8)} {band(op,3)}	UNDEFINED

# A5.2.11
(cond:4)00110(op)10(op1:4)(:8)(op2:8)	{ne(cond,15)} {lnot(op)} {lnot(op1)} {gt(op2,4)} {lt(op2,0xf0)}	UNALLOCATED_HINT

# A5.2.12
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(op2,1)} {lnot(band(op,1))}	UNDEFINED
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(band(op2,6),2)} {ne(op,1)}	UNDEFINED
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(op2,4)}	UNDEFINED
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(op2,6)} {ne(op,3)}	UNDEFINED
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4)	{ne(cond,15)} {eq(op2,7)} {lnot(op)}	UNDEFINED

# A5.4
(cond:4)011(op1:5)(:4)(Rd:4)(:4)(op2:3)1(Rn:4)	{lt(cond,14)} {eq(op1,31)} {eq(op2,7)}	PERMA_UNDEFINED
(cond:4)011(op1:5)(:4)(Rd:4)(:4)(op2:3)1(Rn:4)	{ne(cond,15)} {eq(op1,24)} {op2}	UNDEFINED
(cond:4)011(op1:5)(:4)(Rd:4)(:4)(op2:3)1(Rn:4)	{ne(cond,15)} {eq(op1,25)}	UNDEFINED
(cond:4)011(op1:5)(:4)(Rd:4)(:4)(op2:3)1(Rn:4)	{ne(cond,15)} {eq(band(op1,0x1e),0x1a)} {ne(band(op2,3),2)}	UNDEFINED
(cond:4)011(op1:5)(:4)(Rd:4)(:4)(op2:3)1(Rn:4)	{ne(cond,15)} {eq(band(op1,0x1e),0x1c)} {band(op2,3)}	UNDEFINED
(cond:4)011(op1:5)(:4)(Rd:4)(:4)(op2:3)1(Rn:4)	{ne(cond,15)} {eq(op1,0x1e)} {ne(band(op2,3),2)}	UNDEFINED
(cond:4)011(op1:5)(:4)(Rd:4)(:4)(op2:3)1(Rn:4)	{ne(cond,15)} {eq(op1,31)} {ne(op2,7)} {ne(band(op2,3),2)}	UNDEFINED

# A5.4.1
(cond:4)011000(op1:2)(:12)(op2:3)1(:4)	{ne(cond,15)} {lnot(op1)}	UNDEFINED
(cond:4)011000(op1:2)(:12)(op2:3)1(:4)	{ne(cond,15)} {op1} {lor(eq(op2,5),eq(op2,6))}	UNDEFINED

# A5.4.2
(cond:4)011001(op1:2)(:12)(op2:3)1(:4)	{ne(cond,15)} {lnot(op1)}	UNDEFINED
(cond:4)011001(op1:2)(:12)(op2:3)1(:4)	{ne(cond,15)} {op1} {lor(eq(op2,5),eq(op2,6))}	UNDEFINED

# A5.4.3
(cond:4)01101(op1:3)(A:4)(:8)(op2:3)1(:4)	{ne(cond,15)} {lnot(op1)} {lor(eq(op2,1),eq(op2,7))}	UNDEFINED
(cond:4)01101(op1:3)(A:4)(:8)(op2:3)1(:4)	{ne(cond,15)} {eq(band(op1,3),1)}	UNDEFINED
(cond:4)01101(op1:3)(A:4)(:8)(op2:3)1(:4)	{ne(cond,15)} {eq(band(op1,3),2)} {eq(band(op2,5),5)}	UNDEFINED
(cond:4)01101(op1:3)(A:4)(:8)(op2:3)1(:4)	{ne(cond,15)} {eq(band(op1,3),3)} {eq(op2,7)}	UNDEFINED
(cond:4)01101(op1:3)(A:4)(:8)(op2:3)1(:4)	{ne(cond,15)} {eq(op1,4)} {ne(op2,3)}	UNDEFINED

# A5.4.4
(cond:4)01110(op1:3)(:4)(A:4)(:4)(op2:3)1(:4)	{ne(cond,15)} {lnot(band(op1,3))} {band(op2,4)}	UNDEFINED
(cond:4)01110(op1:3)(:4)(A:4)(:4)(op2:3)1(:4)	{ne(cond,15)} {eq(band(op1,5),1)} {op2}	UNDEFINED
(cond:4)01110(op1:3)(:4)(A:4)(:4)(op2:3)1(:4)	{ne(cond,15)} {band(op1,2)} {ne(op1,3)}	UNDEFINED
(cond:4)01110(op1:3)(:4)(A:4)(:4)(op2:3)1(:4)	{ne(cond,15)} {eq(op1,5)} {band(op2,6)} {lt(op2,6)}	UNDEFINED

# A5.6
#(cond:4)11(op1:6)(Rn:4)(:4)(coproc:4)(:3)(op)(:4)	{ne(cond,15)} {lt(op1,2)}	UNDEFINED # - covered by LDC/STC

# A5.7
1111(op1:8)(Rn:4)(:11)(op)(:4)	{eq(band(op1,0xe5),0x80)}	UNDEFINED
1111(op1:8)(Rn:4)(:11)(op)(:4)	{eq(band(op1,0xe5),0x85)}	UNDEFINED
#1111(op1:8)(Rn:4)(:11)(op)(:4)	{eq(band(op1,0xfb),0xc3)} {eq(Rn,15)}	UNDEFINED # - covered by LDC2/STC2
#1111(op1:8)(Rn:4)(:11)(op)(:4)	{eq(band(op1,0xfe),0xc0)}	UNDEFINED # - covered by LDC2/STC2
#1111(op1:8)(Rn:4)(:11)(op)(:4)	{eq(band(op1,0xf9),0xc9)} {ne(Rn,15)}	UNDEFINED # - covered by LDC2/STC2
#1111(op1:8)(Rn:4)(:11)(op)(:4)	{eq(band(op1,0xf1),0xd1)} {ne(Rn,15)}	UNDEFINED # - covered by LDC2/STC2
1111(op1:8)(Rn:4)(:11)(op)(:4)	{eq(band(op1,0xf0),0xf0)}	UNDEFINED

# A5.7.1
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{lt(op1,16)}	UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{eq(op1,16)} {lnot(band(Rn,1))} {band(op2,2)}	UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{eq(op1,16)} {band(Rn,1)} {op2}	UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{gt(op1,16)} {lt(op1,32)}	UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{eq(band(op1,0x77),0x41)}	UNALLOCATED_MEM_HINT
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{eq(band(op1,0x77),0x50)}	UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{eq(band(op1,0x77),0x51)} {eq(Rn,15)}	UNPREDICTABLE
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{ge(band(op1,0x77),0x52)} {le(band(op1,0x77),0x56)} {lnot(band(op1,1))}	UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{eq(op1,0x57)} {ne(op2,1)} {lor(lt(op2,4),gt(op2,6))}	UNPREDICTABLE
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{eq(band(op1,0x63),0x43)} {ne(op1,0x57)}	UNPREDICTABLE
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{eq(band(op1,0x77),0x61)} {lnot(band(op2,1))}	UNALLOCATED_MEM_HINT
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{eq(band(op1,0x61),0x60)}	UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{eq(band(op1,0x61),0x61)} {band(op2,1)}	UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4)	{eq(band(op1,0x63),0x63)} {lnot(band(op2,1))}	UNPREDICTABLE


# A8.8.1 ADC (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0010101S(Rn:4)(Rd:4)(imm12:12)			{ne(cond,15)}	ADC_imm_A1 # NOTE: Action must handle "SUBS PC, LR and related instructions"

# A8.8.2 ADC (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000101S(Rn:4)(Rd:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	ADC_reg_A1 # NOTE: Action must handle "SUBS PC, LR and related instructions"

# A8.8.3 ADC (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000101S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	ADC_rsr_A1

# A8.8.5 ADD (immediate, ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0010100S(Rn:4)(Rd:4)(imm12:12)			{ne(cond,15)} {lor(ne(Rn,15),ne(S,0))} {ne(Rn,13)}	ADD_imm_A1 # NOTE: Action must handle "SUBS PC, LR and related instructions"

# A8.8.7 ADD (register, ARM)
# A1 ARMv4*, ARMv5t*, ARMv6*, ARMv7
(cond:4)0000100S(Rn:4)(Rd:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)} {ne(Rn,13)}	ADD_reg_A1 # NOTE: Action must handle "SUBS PC, LR and related instructions"

# A8.8.8 ADD (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000100S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	ADD_rsr_A1

# A8.8.9 ADD (SP plus immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0010100S1101(Rd:4)(imm12:12)			{ne(cond,15)}	ADD_sp_imm_A1 # NOTE: Action must handle "SUBS PC, LR and related instructions"

# A8.8.11 ADD (SP plus register, ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000100S1101(Rd:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	ADD_sp_reg_A1 # NOTE: Action must handle "SUBS PC, LR and related instructions"

# A8.8.12 ADR
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)001010001111(Rd:4)(imm12:12)			{ne(cond,15)}	ADR_A1
# A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)001001001111(Rd:4)(imm12:12)			{ne(cond,15)}	ADR_A2

# A8.8.13 AND (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0010000S(Rn:4)(Rd:4)(imm12:12)			{ne(cond,15)}	AND_imm_A1 # NOTE: Action must handle "SUBS PC, LR and related instructions"

# A8.8.14 AND (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000000S(Rn:4)(Rd:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	AND_reg_A1 # NOTE: SUBS PC, LR

# A8.8.15 AND (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000000S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	AND_rsr_A1

# A8.8.16 ASR (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001101S(0000)(Rd:4)(imm5:5)100(Rm:4)	{ne(cond,15)}	ASR_imm_A1

# A8.8.17 ASR (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001101S(0000)(Rd:4)(Rm:4)0101(Rn:4)	{ne(cond,15)}	ASR_reg_A1

# A8.8.18 B
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)1010(imm24:24)	{ne(cond,15)}	B_A1

# A8.8.19 BFC
# A1 ARMv6T2, ARMv7
(cond:4)0111110(msb:5)(Rd:4)(lsb:5)0011111	{ne(cond,15)}	BFC_A1

# A8.8.20 BFI
# A1 ARMv6T2, ARMv7
(cond:4)0111110(msb:5)(Rd:4)(lsb:5)001(Rn:4)	{ne(cond,15)} {ne(Rn,15)}	BFI_A1

# A8.8.21 BIC (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0011110S(Rn:4)(Rd:4)(imm12:12)		{ne(cond,15)}	BIC_imm_A1 # NOTE: SUBS PC, LR

# A8.8.22 BIC (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001110S(Rn:4)(Rd:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	BIC_reg_A1 # NOTE: SUBS PC, LR

# A8.8.23 BIC (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001110S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	BIC_rsr_A1

# A8.8.24 BKPT
# A1 ARMv5T*, ARMv6*, ARMv7
(cond:4)00010010(imm12:12)0111(imm4:4)	{ne(cond,15)}	BKPT_A1

# A8.8.25 BL, BLX (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)1011(imm24:24)	{ne(cond,15)}	BL_BLX_imm_A1
# A2 ARMv5T*, ARMv6*, ARMv7
1111101H(imm24:24)	BL_BLX_imm_A2

# A8.8.26 BLX (register)
# A1 ARMv5T*, ARMv6*, ARMv7
(cond:4)00010010(111111111111)0011(Rm:4)	{ne(cond,15)}	BLX_reg_A1

# A8.8.27 BX
# A1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
(cond:4)00010010(111111111111)0001(Rm:4)	{ne(cond,15)}	BX_A1

# A8.8.28 BXJ
# A1 ARMv5TEJ, ARMv6*, ARMv7
(cond:4)00010010(111111111111)0010(Rm:4)	{ne(cond,15)}	BXJ_A1

# A8.8.30 CDP, CDP2
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)1110(opc1:4)(CRn:4)(CRd:4)(coproc:4)(opc2:3)0(CRm:4)	{ne(cond,15)} {ne(coproc,10)} {ne(coproc,11)} [CDP]	CDP_CDP2_A1
# A2 ARMv5T*, ARMv6T*, ARMv7
11111110(opc1:4)(CRn:4)(CRd:4)(coproc:4)(opc2:3)0(CRm:4)	CDP_CDP2_A2

# A8.8.32 CLREX
# A1 ARMv6K, ARMv7
111101010111(111111110000)0001(1111)	CLREX_A1

# A8.8.33 CLZ
# A1 ARMv5T*, ARMv6*, ARMv7
(cond:4)00010110(1111)(Rd:4)(1111)0001(Rm:4)	{ne(cond,15)}	CLZ_A1

# A8.8.34 CMN (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00110111(Rn:4)(0000)(imm12:12)		{ne(cond,15)}	CMN_imm_A1

# A8.8.35 CMN (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00010111(Rn:4)(0000)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	CMN_reg_A1

# A8.8.36 CMN (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00010111(Rn:4)(0000)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	CMN_rsr_A1

# A8.8.37 CMP (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00110101(Rn:4)(0000)(imm12:12)	{ne(cond,15)}	CMP_imm_A1

# A8.8.38 CMP (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00010101(Rn:4)(0000)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	CMP_reg_A1

# A8.8.39 CMP (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00010101(Rn:4)(0000)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	CMP_rsr_A1

# A8.8.42 DBG
# A1 ARMv7
(cond:4)001100100000(11110000)1111(option:4)	{ne(cond,15)}	DBG_A1

# A8.8.43 DMB
# A1 ARMv7
111101010111(111111110000)0101(option:4)	DMB_A1

# A8.8.44 DSB
# A1 ARMv7
111101010111(111111110000)0100(option:4)	DSB_A1

# A8.8.46 EOR (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0010001S(Rn:4)(Rd:4)(imm12:12)	{ne(cond,15)}	EOR_imm_A1 # NOTE: SUBS PC, LR

# A8.8.47 EOR (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000001S(Rn:4)(Rd:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	EOR_reg_A1 # NOTE: SUBS PC, LR

# A8.8.48 EOR (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000001S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	EOR_rsr_A1

# A8.8.53 ISB
# A1 ARMv7
111101010111(111111110000)0110(option:4)	ISB_A1

# A8.8.55 LDC, LDC2 (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)11000001(Rn:4)(CRd:4)(coproc:4)(imm8:8)	{ne(cond,15)} {ne(Rn,15)} {ne(coproc,10)} {ne(coproc,11)} [LDC_STC]	UNDEFINED
(cond:4)110PUDW1(Rn:4)(CRd:4)(coproc:4)(imm8:8)	{ne(cond,15)} {ne(Rn,15)} {ne(coproc,10)} {ne(coproc,11)} {lor(lor(P,U),W)} [LDC_STC]	LDC_LDC2_imm_A1
# A2 ARMv5T*, ARMv6*, ARMv7
111111000001(Rn:4)(CRd:4)(coproc:4)(imm8:8)	{ne(Rn,15)}	UNDEFINED
1111110PUDW1(Rn:4)(CRd:4)(coproc:4)(imm8:8)	{ne(Rn,15)} {lor(lor(P,U),W)}	LDC_LDC2_imm_A2

# A8.8.56 LDC, LDC2 (literal)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)110000011111(CRd:4)(coproc:4)(imm8:8)	{ne(cond,15)} {ne(coproc,10)} {ne(coproc,11)} [LDC_STC]	UNDEFINED
(cond:4)110PUDW11111(CRd:4)(coproc:4)(imm8:8)	{ne(cond,15)} {ne(coproc,10)} {ne(coproc,11)} {lor(lor(P,U),W)} [LDC_STC]	LDC_LDC2_lit_A1
# A2, ARMv5T*, ARMv6*, ARMv7
1111110000011111(CRd:4)(coproc:4)(imm8:8)		UNDEFINED
1111110PUDW11111(CRd:4)(coproc:4)(imm8:8)	{lor(lor(P,U),W)}	LDC_LDC2_lit_A2

# A8.8.58 LDM/LDMIA/LDMFD (ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)100010W1(Rn:4)(reglist:16)	{ne(cond,15)} {lor(lor(ne(W,1),ne(Rn,13)),lt(bitcount(reglist),2))}	LDMIA_A1

# A8.8.59 LDMDA/LDMFA
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)100000W1(Rn:4)(reglist:16)	{ne(cond,15)} LDMDA_A1

# A8.8.60 LDMDB/LDMEA
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)100100W1(Rn:4)(reglist:16)	{ne(cond,15)} LDMDB_A1

# A8.8.61 LDMIB/LDMED
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)100110W1(Rn:4)(reglist:16)	{ne(cond,15)} LDMIB_A1

# A8.8.63 LDR (immediate, ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)010PU0W1(Rn:4)(Rt:4)(imm12:12)	{ne(cond,15)} {ne(Rn,15)} {lor(P,lnot(W))} {lnot(land(land(land(eq(Rn,13),lnot(P)),land(U,lnot(W))),eq(imm12,4)))}	LDR_imm_A1

# A8.8.64 LDR (literal)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)010(1)U0(0)11111(Rt:4)(imm12:12)	{ne(cond,15)} {lor(opcode<24>,lnot(opcode<21>))}	LDR_lit_A1 # Note manual disambiguation (see A5.3)

# A8.8.66 LDR (register, ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)011PU0W1(Rn:4)(Rt:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)} {lor(P,lnot(W))}	LDR_reg_A1

# A8.8.68 LDRB (immediate, ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)010PU1W1(Rn:4)(Rt:4)(imm12:12)	{ne(cond,15)} {ne(Rn,15)} {lor(P,lnot(W))}	LDRB_imm_A1

# A8.8.69 LDRB (literal)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)010(1)U1(0)11111(Rt:4)(imm12:12)	{ne(cond,15)} {lor(opcode<24>,lnot(opcode<21>))}	LDRB_lit_A1 # Note manual disambiguation (see A5.3)

# A8.8.70 LDRB (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)011PU1W1(Rn:4)(Rt:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)} {lor(P,lnot(W))}	LDRB_reg_A1

# A8.8.71 LDRBT
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0100U111(Rn:4)(Rt:4)(imm12:12)	{ne(cond,15)}	LDRBT_A1
# A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0110U111(Rn:4)(Rt:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	LDRBT_A2

# A8.8.72 LDRD (immediate)
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)000PU1W0(Rn:4)(Rt:4)(imm4H:4)1101(imm4L:4)	{ne(cond,15)} {ne(Rn,15)} {lor(opcode<24>,lnot(opcode<21>))}	LDRD_imm_A1 # Note manual disambiguation (see A5.2)

# A8.8.73 LDRD (literal)
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)000(1)U1(0)01111(Rt:4)(imm4H:4)1101(imm4L:4)	{ne(cond,15)} {lor(opcode<24>,lnot(opcode<21>))}	LDRD_lit_A1 # Note manual disambiguation (see A5.2)

# A8.8.74 LDRD (register)
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)000PU0W0(Rn:4)(Rt:4)(0000)1101(Rm:4)	{ne(cond,15)} {lor(opcode<24>,lnot(opcode<21>))}	LDRD_reg_A1 # Note manual disambiguation (see A5.2)

# A8.8.75 LDREX
# A1 ARMv6*, ARMv7
(cond:4)00011001(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREX_A1

# A8.8.76 LDREXB
# A1 ARMv6K, ARMv7
(cond:4)00011101(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREXB_A1

# A8.8.77 LDREXD
# A1 ARMv6K, ARMv7
(cond:4)00011011(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREXD_A1

# A8.8.78 LDREXH
# A1 ARMv6K, ARMv7
(cond:4)00011111(Rn:4)(Rt:4)(1111)1001(1111)	{ne(cond,15)}	LDREXH_A1

# A8.8.80 LDRH (immediate, ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)000PU1W1(Rn:4)(Rt:4)(imm4H:4)1011(imm4L:4)	{ne(cond,15)} {ne(Rn,15)} {lor(P,lnot(W))}	LDRH_imm_A1

# A8.8.81 LDRH (literal)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)000(1)U1(0)11111(Rt:4)(imm4H:4)1011(imm4L:4)	{ne(cond,15)} {lor(opcode<24>,lnot(opcode<21>))}	LDRH_lit_A1 # Note manual disambiguation (see A5.2)

# A8.8.82 LDRH (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)000PU0W1(Rn:4)(Rt:4)(0000)1011(Rm:4)	{ne(cond,15)} {lor(P,lnot(W))}	LDRH_reg_A1

# A8.8.83 LDRHT
# A1 ARMv6T2, ARMv7
(cond:4)0000U111(Rn:4)(Rt:4)(imm4H:4)1011(imm4L:4)	{ne(cond,15)}	LDRHT_A1
# A2 ARMv6T2, ARMv7
(cond:4)0000U011(Rn:4)(Rt:4)(0000)1011(Rm:4)	{ne(cond,15)}	LDRHT_A2

# A8.8.85 LDRSB (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)000PU1W1(Rn:4)(Rt:4)(imm4H:4)1101(imm4L:4)	{ne(cond,15)} {ne(Rn,15)} {lor(P,lnot(W))}	LDRSB_imm_A1

# A8.8.85 LDRSB (literal)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)000(1)U1(0)11111(Rt:4)(imm4H:4)1101(imm4L:4)	{ne(cond,15)} {lor(opcode<24>,lnot(opcode<21>))}	LDRSB_lit_A1 # Note manual disambiguation (see A5.2)

# A8.8.86 LDRSB (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)000PU0W1(Rn:4)(Rt:4)(0000)1101(Rm:4)	{ne(cond,15)} {lor(P,lnot(W))}	LDRSB_reg_A1

# A8.8.87 LDRSBT
# A1 ARMv6T2, ARMv7
(cond:4)0000U111(Rn:4)(Rt:4)(imm4H:4)1101(imm4L:4)	{ne(cond,15)}	LDRSBT_A1
# A2 ARMv6T2, ARMv7
(cond:4)0000U011(Rn:4)(Rt:4)(0000)1101(Rm:4)	{ne(cond,15)}	LDRSBT_A2

# A8.8.88 LDRSH (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)000PU1W1(Rn:4)(Rt:4)(imm4H:4)1111(imm4L:4)	{ne(cond,15)} {ne(Rn,15)} {lor(P,lnot(W))}	LDRSH_imm_A1

# A8.8.89 LDRSH (literal)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)000(1)U1(0)11111(Rt:4)(imm4H:4)1111(imm4L:4)	{ne(cond,15)} {lor(opcode<24>,lnot(opcode<21>))}	LDRSH_lit_A1 # Note manual disambiguation (see A5.2)

# A8.8.90 LDRSH (register)
# A1 ARMv4*, ARMv4T*, ARMv6*, ARMv7
(cond:4)000PU0W1(Rn:4)(Rt:4)(0000)1111(Rm:4)	{ne(cond,15)} {lor(P,lnot(W))}	LDRSH_reg_A1

# A8.8.91 LDRSHT
# A1 ARMv6T2, ARMv7
(cond:4)0000U111(Rn:4)(Rt:4)(imm4H:4)1111(imm4L:4)	{ne(cond,15)}	LDRSHT_A1
# A2 ARMv6T2, ARMv7
(cond:4)0000U011(Rn:4)(Rt:4)(0000)1111(Rm:4)	{ne(cond,15)}	LDRSHT_A2

# A8.8.92 LDRT
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0100U011(Rn:4)(Rt:4)(imm12:12)	{ne(cond,15)}	LDRT_A1
# A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0110U011(Rn:4)(Rt:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	LDRT_A2

# A8.8.94 LSL (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001101S(0000)(Rd:4)(imm5:5)000(Rm:4)	{ne(cond,15)} {imm5}	LSL_imm_A1

# A8.8.95 LSL (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001101S(0000)(Rd:4)(Rm:4)0001(Rn:4)	{ne(cond,15)}	LSL_reg_A1

# A8.8.96 LSR (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001101S(0000)(Rd:4)(imm5:5)010(Rm:4)	{ne(cond,15)}	LSR_imm_A1

# A8.8.97 LSR (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001101S(0000)(Rd:4)(Rm:4)0011(Rn:4)	{ne(cond,15)}	LSR_reg_A1

# A8.8.98 MCR, MCR2
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)1110(opc1:3)0(CRn:4)(Rt:4)(coproc:4)(opc2:3)1(CRm:4)	{ne(cond,15)} {ne(coproc,10)} {ne(coproc,11)} [MRC_MCR]	MCR_MCR2_A1
# A2 ARMv5T*, ARMv6*, ARMv7
11111110(opc1:3)0(CRn:4)(Rt:4)(coproc:4)(opc2:3)1(CRm:4)	MCR_MCR2_A2

# A8.8.99 MCRR, MCRR2
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)11000100(Rt2:4)(Rt:4)(coproc:4)(opc1:4)(CRm:4)	{ne(cond,15)} {ne(coproc,10)} {ne(coproc,11)} [LDC_STC]	MCRR_MCRR2_A1
# A2 ARMv6*, ARMv7
111111000100(Rt2:4)(Rt:4)(coproc:4)(opc1:4)(CRm:4)	MCRR_MCRR2_A2

# A8.8.100 MLA
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000001S(Rd:4)(Ra:4)(Rm:4)1001(Rn:4)	{ne(cond,15)}	MLA_A1

# A8.8.101 MLS
# A1 ARMv6T2, ARMv7
(cond:4)00000110(Rd:4)(Ra:4)(Rm:4)1001(Rn:4)	{ne(cond,15)}	MLS_A1

# A8.8.102 MOV (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0011101S(0000)(Rd:4)(imm12:12)	{ne(cond,15)}	MOV_imm_A1 # NOTE: SUBS PC, LR
# A2 ARMv6T2, ARMv7
(cond:4)00110000(imm4:4)(Rd:4)(imm12:12)	{ne(cond,15)}	MOV_imm_A2

# A8.8.104 MOV (register, ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001101S(0000)(Rd:4)00000000(Rm:4)	{ne(cond,15)}	MOV_reg_A1 # NOTE: SUBS PC, LR

# A8.8.106 MOVT
# A1 ARMv6T2, ARMv7
(cond:4)00110100(imm4:4)(Rd:4)(imm12:12)	{ne(cond,15)}	MOVT_A1

# A8.8.107 MRC, MRC2
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)1110(opc1:3)1(CRn:4)(Rt:4)(coproc:4)(opc2:3)1(CRm:4)	{ne(cond,15)} {ne(coproc,10)} {ne(coproc,11)} [MRC_MCR]	MRC_MRC2_A1
# A2 ARMv5T*, ARMv6*, ARMv7
11111110(opc1:3)1(CRn:4)(Rt:4)(coproc:4)(opc2:3)1(CRm:4)	MRC_MRC2_A2

# A8.8.108 MRRC, MRRC2
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)11000101(Rt2:4)(Rt:4)(coproc:4)(opc1:4)(CRm:4)	{ne(cond,15)} {ne(coproc,10)} {ne(coproc,11)} [LDC_STC]	MRRC_MRRC2_A1
# A2 ARMv6*, ARMv7
111111000101(Rt2:4)(Rt:4)(coproc:4)(opc1:4)(CRm:4)	MRRC_MRRC2_A2

# A8.8.109 MRS
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
#(cond:4)00010000(1111)(Rd:4)(0000)0000(0000)	{ne(cond,15)}	MRS_A1 # - covered by B6.1.5

# A8.8.111 MSR (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
#(cond:4)00110010(mask:2)00(1111)(imm12:12)	{ne(cond,15)} {mask}	MSR_imm_A1 # - covered by B6.1.6

# A8.8.112 MSR (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
#(cond:4)00010010(mask:2)00(11110000)0000(Rn:4)	{ne(cond,15)}	MSR_reg_A1 # - covered by B6.1.7

# A8.8.114 MUL
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000000S(Rd:4)(0000)(Rm:4)1001(Rn:4)	{ne(cond,15)}	MUL_A1

# A8.8.115 MVN (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0011111S(0000)(Rd:4)(imm12:12)	{ne(cond,15)}	MVN_imm_A1 # NOTE: SUBS PC, LR

# A8.8.116 MVN (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001111S(0000)(Rd:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	MVN_reg_A1 # NOTE: SUBS PC, LR

# A8.8.117 MVN (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001111S(0000)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	MVN_rsr_A1

# A8.8.119 NOP
# A1 ARMv6K, ARMv6T2, ARMv7
(cond:4)001100100000(11110000)00000000	{ne(cond,15)}	NOP_A1

# A8.8.122 ORR (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0011100S(Rn:4)(Rd:4)(imm12:12)	{ne(cond,15)}	ORR_imm_A1 # NOTE: SUBS PC, LR

# A8.8.123 ORR (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001100S(Rn:4)(Rd:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	ORR_reg_A1 # NOTE: SUBS PC, LR

# A8.8.124 ORR (register-shfited register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001100S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	ORR_rsr_A1

# A8.8.125 PKH
# A1 ARMv6*, ARMv7
(cond:4)01101000(Rn:4)(Rd:4)(imm5:5)(tb)01(Rm:4)	{ne(cond,15)}	PKH_A1

# A8.8.126 PLD, PLDW (immediate)
# A1 ARMv5TE*, ARMv6*, ARMv7
11110101UR01(Rn:4)(1111)(imm12:12)	{ne(Rn,15)} {R}	PLD_imm_A1a
# A1 ARMv7MP
11110101UR01(Rn:4)(1111)(imm12:12)	{ne(Rn,15)} {lnot(R)}	PLD_imm_A1b

# A8.8.127 PLD (literal)
# A1 ARMv5TE*, ARMv6*, ARMv7
11110101U1011111(1111)(imm12:12)	PLD_lit_A1 # Note that the ARM shows bit 22 as (1), not 1. Fixing it to 1 avoids it matching against the defined UNPREDICTABLE block in A5.7.1 (although PLD with bit 22==0 should be treated as unpredictable anyway)

# A8.8.128 PLD, PLDW (register)
# A1 ARMv5TE*, ARMv6*, ARMv7
11110111UR01(Rn:4)(1111)(imm5:5)(type:2)0(Rm:4)	{R}	PLD_reg_A1a
# A1 ARMv7MP
11110111UR01(Rn:4)(1111)(imm5:5)(type:2)0(Rm:4)	{lnot(R)}	PLD_reg_A1b

# A8.8.129 PLI (immediate, literal)
# A1 ARMv7
11110100U101(Rn:4)(1111)(imm12:12)	PLI_imm_lit_A1

# A8.8.130 PLI (register)
# A1 ARMv7
11110110U101(Rn:4)(1111)(imm5:5)(type:2)0(Rm:4)	PLI_reg_A1

# A8.8.132 POP (ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)100010111101(reglist:16)	{ne(cond,15)} {ge(bitcount(reglist),2)}	POP_A1
# A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)010010011101(Rt:4)000000000100	{ne(cond,15)}	POP_A2

# A8.8.133 PUSH (ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)100100101101(reglist:16)	{ne(cond,15)} {ge(bitcount(reglist),2)}	PUSH_A1
# A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)010100101101(Rt:4)000000000100	{ne(cond,15)}	PUSH_A2

# A8.8.134 QADD
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)00010000(Rn:4)(Rd:4)(0000)0101(Rm:4)	{ne(cond,15)}	QADD_A1

# A8.8.135 QADD16
# A1 ARMv6*, ARMv7
(cond:4)01100010(Rn:4)(Rd:4)(1111)0001(Rm:4)	{ne(cond,15)}	QADD16_A1

# A8.8.136 QADD8
# A1 ARMv6*, ARMv7
(cond:4)01100010(Rn:4)(Rd:4)(1111)1001(Rm:4)	{ne(cond,15)}	QADD8_A1

# A8.8.137 QASX
# A1 ARMv6*, ARMv7
(cond:4)01100010(Rn:4)(Rd:4)(1111)0011(Rm:4)	{ne(cond,15)}	QASX_A1

# A8.8.138 QDADD
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)00010100(Rn:4)(Rd:4)(0000)0101(Rm:4)	{ne(cond,15)}	QDADD_A1

# A8.8.139 QDSUB
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)00010110(Rn:4)(Rd:4)(0000)0101(Rm:4)	{ne(cond,15)}	QDSUB_A1

# A8.8.140 QSAX
# A1 ARMv6*, ARMv7
(cond:4)01100010(Rn:4)(Rd:4)(1111)0101(Rm:4)	{ne(cond,15)}	QSAX_A1

# A8.8.141 QSUB
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)00010010(Rn:4)(Rd:4)(0000)0101(Rm:4)	{ne(cond,15)}	QSUB_A1

# A8.8.142 QSUB16
# A1 ARMv6*, ARMv7
(cond:4)01100010(Rn:4)(Rd:4)(1111)0111(Rm:4)	{ne(cond,15)}	QSUB16_A1

# A8.8.143 QSUB8
# A1 ARMv6*, ARMv7
(cond:4)01100010(Rn:4)(Rd:4)(1111)1111(Rm:4)	{ne(cond,15)}	QSUB8_A1

# A8.8.144 RBIT
# A1 ARMv6T2, ARMv7
(cond:4)01101111(1111)(Rd:4)(1111)0011(Rm:4)	{ne(cond,15)}	RBIT_A1

# A8.8.145 REV
# A1 ARMv6*, ARMv7
(cond:4)01101011(1111)(Rd:4)(1111)0011(Rm:4)	{ne(cond,15)}	REV_A1

# A8.8.146 REV16
# A1 ARMv6*, ARMv7
(cond:4)01101011(1111)(Rd:4)(1111)1011(Rm:4)	{ne(cond,15)}	REV16_A1

# A8.8.147 REVSH
# A1 ARMv6*, ARMv7
(cond:4)01101111(1111)(Rd:4)(1111)1011(Rm:4)	{ne(cond,15)}	REVSH_A1

# A8.8.149 ROR (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001101S(0000)(Rd:4)(imm5:5)110(Rm:4)	{ne(cond,15)} {imm5}	ROR_imm_A1

# A8.8.150 ROR (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001101S(0000)(Rd:4)(Rm:4)0111(Rn:4)	{ne(cond,15)}	ROR_reg_A1

# A8.8.151 RRX
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0001101S(0000)(Rd:4)00000110(Rm:4)	{ne(cond,15)}	RRX_A1

# A8.8.152 RSB (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0010011S(Rn:4)(Rd:4)(imm12:12)	{ne(cond,15)}	RSB_imm_A1

# A8.8.153 RSB (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000011S(Rn:4)(Rd:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	RSB_reg_A1 # NOTE: SUBS PC, LR

# A8.8.154 RSB (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000011S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	RSB_rsr_A1

# A8.8.155 RSC (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0010111S(Rn:4)(Rd:4)(imm12:12)	{ne(cond,15)}	RSC_imm_A1

# A8.8.156 RSC (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000111S(Rn:4)(Rd:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	RSC_reg_A1 # NOTE: SUBS PC, LR

# A8.8.157 RSC (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv5*, ARMv7
(cond:4)0000111S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	RSC_rsr_A1

# A8.8.158 SADD16
# A1 ARMv6*, ARMv7
(cond:4)01100001(Rn:4)(Rd:4)(1111)0001(Rm:4)	{ne(cond,15)}	SADD16_A1

# A8.8.159 SADD8
# A1 ARMv6*, ARMv7
(cond:4)01100001(Rn:4)(Rd:4)(1111)1001(Rm:4)	{ne(cond,15)}	SADD8_A1

# A8.8.160 SASX
# A1 ARMv6*, ARMv7
(cond:4)01100001(Rn:4)(Rd:4)(1111)0011(Rm:4)	{ne(cond,15)}	SASX_A1

# A8.8.161 SBC (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0010110S(Rn:4)(Rd:4)(imm12:12)	{ne(cond,15)}	SBC_imm_A1 # NOTE: SUBS PC, LR

# A8.8.162 SBC (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000110S(Rn:4)(Rd:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	SBC_reg_A1 # NOTE: SUBS PC, LR

# A8.8.163 SBC (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000110S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	SBC_rsr_A1

# A8.8.164 SBFX
# A1 ARMv6T2, ARMv7
(cond:4)0111101(widthm1:5)(Rd:4)(lsb:5)101(Rn:4)	{ne(cond,15)}	SBFX_A1

# A8.8.165 SDIV
# A1 ARMv7VE, ARMv7opt
(cond:4)01110001(Rd:4)(1111)(Rm:4)0001(Rn:4)	{ne(cond,15)}	SDIV_A1

# A8.8.166 SEL
# A1 ARMv6*, ARMv7
(cond:4)01101000(Rn:4)(Rd:4)(1111)1011(Rm:4)	{ne(cond,15)}	SEL_A1

# A8.8.167 SETEND
# A1 ARMv6*, ARMv7
111100010000(000)1(000000)E(0)0000(0000)	SETEND_A1

# A8.8.168 SEV
# A1 ARMv7
(cond:4)001100100000(11110000)00000100	{ne(cond,15)}	SEV_A1

# A8.8.169 SHADD16
# A1 ARMv6*, ARMv7
(cond:4)01100011(Rn:4)(Rd:4)(1111)0001(Rm:4)	{ne(cond,15)}	SHADD16_A1

# A8.8.170 SHADD8
# A1 ARMv6*, ARMv7
(cond:4)01100011(Rn:4)(Rd:4)(1111)1001(Rm:4)	{ne(cond,15)}	SHADD8_A1

# A8.8.171 SHASX
# A1 ARMv6*, ARMv7
(cond:4)01100011(Rn:4)(Rd:4)(1111)0011(Rm:4)	{ne(cond,15)}	SHASX_A1

# A8.8.172 SHSAX
# A1 ARMv6*, ARMv7
(cond:4)01100011(Rn:4)(Rd:4)(1111)0101(Rm:4)	{ne(cond,15)}	SHSAX_A1

# A8.8.173 SHSUB16
# A1 ARMv6*, ARMv7
(cond:4)01100011(Rn:4)(Rd:4)(1111)0111(Rm:4)	{ne(cond,15)}	SHSUB16_A1

# A8.8.174 SHSUB8
# A1 ARMv6*, ARMv7
(cond:4)01100011(Rn:4)(Rd:4)(1111)1111(Rm:4)	{ne(cond,15)}	SHSUB8_A1

# A8.8.176 SMLABB, SMLABT, SMLATB, SMLATT
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)00010000(Rd:4)(Ra:4)(Rm:4)1MN0(Rn:4)	{ne(cond,15)}	SMLAxx_A1

# A8.8.177 SMLAD
# A1 ARMv6*, ARMv7
(cond:4)01110000(Rd:4)(Ra:4)(Rm:4)00M1(Rn:4)	{ne(cond,15)} {ne(Ra,15)}	SMLAD_A1

# A8.8.178 SMLAL
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000111S(RdHi:4)(RdLo:4)(Rm:4)1001(Rn:4)	{ne(cond,15)}	SMLAL_A1

# A8.8.179 SMLALBB, SMLALBT, SMLALTB, SMLALTT
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)00010100(RdHi:4)(RdLo:4)(Rm:4)1MN0(Rn:4)	{ne(cond,15)}	SMLALxx_A1

# A8.8.180 SMLALD
# A1 ARMv6*, ARMv7
(cond:4)01110100(RdHi:4)(RdLo:4)(Rm:4)00M1(Rn:4)	{ne(cond,15)}	SMLALD_A1

# A8.8.181 SMLAWB, SMLAWT
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)00010010(Rd:4)(Ra:4)(Rm:4)1M00(Rn:4)	{ne(cond,15)}	SMLAWx_A1

# A8.8.182 SMLSD
# A1 ARMv6*, ARMv7
(cond:4)01110000(Rd:4)(Ra:4)(Rm:4)01M1(Rn:4)	{ne(cond,15)} {ne(Ra,15)}	SMLSD_A1

# A8.8.183 SMLSLD
# A1 ARMv6*, ARMv7
(cond:4)01110100(RdHi:4)(RdLo:4)(Rm:4)01M1(Rn:4)	{ne(cond,15)}	SMLSLD_A1

# A8.8.184 SMMLA
# A1 ARMv6*, ARMv7
(cond:4)01110101(Rd:4)(Ra:4)(Rm:4)00R1(Rn:4)	{ne(cond,15)} {ne(Ra,15)}	SMMLA_A1

# A8.8.185 SMMLS
# A1 ARMv6*, ARMv7
(cond:4)01110101(Rd:4)(Ra:4)(Rm:4)11R1(Rn:4)	{ne(cond,15)}	SMMLS_A1

# A8.8.186 SMMUL
# A1 ARMv6*, ARMv7
(cond:4)01110101(Rd:4)1111(Rm:4)00R1(Rn:4)	{ne(cond,15)}	SMMUL_A1

# A8.8.187 SMUAD
# A1 ARMv6*, ARMv7
(cond:4)01110000(Rd:4)1111(Rm:4)00M1(Rn:4)	{ne(cond,15)}	SMUAD_A1

# A8.8.188 SMULBB, SMULBT, SMULTB, SMULTT
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)00010110(Rd:4)(0000)(Rm:4)1MN0(Rn:4)	{ne(cond,15)}	SMULxx_A1

# A8.8.189 SMULL
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000110S(RdHi:4)(RdLo:4)(Rm:4)1001(Rn:4)	{ne(cond,15)}	SMULL_A1

# A8.8.190 SMULWB, SMULWT
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)00010010(Rd:4)(0000)(Rm:4)1M10(Rn:4)	{ne(cond,15)}	SMULWx_A1

# A8.8.191 SMUSD
# A1 ARMv6*, ARMv7
(cond:4)01110000(Rd:4)1111(Rm:4)01M1(Rn:4)	{ne(cond,15)}	SMUSD_A1

# A8.8.193 SSAT
# A1 ARMv6*, ARMv7
(cond:4)0110101(sat_imm:5)(Rd:4)(imm5:5)(sh)01(Rn:4)	{ne(cond,15)}	SSAT_A1

# A8.8.194 SSAT16
# A1 ARMv6*, ARMv7
(cond:4)01101010(sat_imm:4)(Rd:4)(1111)0011(Rn:4)	{ne(cond,15)}	SSAT16_A1

# A8.8.195 SSAX
# A1 ARMv6*, ARMv7
(cond:4)01100001(Rn:4)(Rd:4)(1111)0101(Rm:4)	{ne(cond,15)}	SSAX_A1

# A8.8.196 SSUB16
# A1 ARMv6*, ARMv7
(cond:4)01100001(Rn:4)(Rd:4)(1111)0111(Rm:4)	{ne(cond,15)}	SSUB16_A1

# A8.8.197 SSUB8
# A1 ARMv6*, ARMv7
(cond:4)01100001(Rn:4)(Rd:4)(1111)1111(Rm:4)	{ne(cond,15)}	SSUB8_A1

# A8.8.198 STC, STC2
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)11000000(Rn:4)(CRd:4)(coproc:4)(imm8:8)	{ne(cond,15)} {ne(coproc,10)} {ne(coproc,11)} [LDC_STC]	UNDEFINED
(cond:4)110PUDW0(Rn:4)(CRd:4)(coproc:4)(imm8:8)	{ne(cond,15)} {lor(lor(P,U),W)} {ne(coproc,10)} {ne(coproc,11)} [LDC_STC]	STC_STC2_A1
# A2 ARMv5T*, ARMv6*, ARMv7
111111000000(Rn:4)(CRd:4)(coproc:4)(imm8:8)	UNDEFINED
1111110PUDW0(Rn:4)(CRd:4)(coproc:4)(imm8:8)	{lor(lor(P,U),W)}	STC_STC2_A2

# A8.8.199 STM/STMIA/STMEA
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)100010W0(Rn:4)(reglist:16)	{ne(cond,15)}	STMIA_A1

# A8.8.200 STMDA/STMED
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)100000W0(Rn:4)(reglist:16)	{ne(cond,15)}	STMDA_A1

# A8.8.201 STMDB/STMFD
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)100100W0(Rn:4)(reglist:16)	{ne(cond,15)} {lor(lor(ne(W,1),ne(Rn,13)),lt(bitcount(reglist),2))}	STMDB_A1

# A8.8.202 STMIB/STMFA
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)100110W0(Rn:4)(reglist:16)	{ne(cond,15)}	STMIB_A1

# A8.8.204 STR (immediate, ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)010PU0W0(Rn:4)(Rt:4)(imm12:12)	{ne(cond,15)} {lor(P,lnot(W))} {lnot(land(land(land(eq(Rn,13),P),land(lnot(U),W)),eq(imm12,4)))}	STR_imm_A1

# A8.8.205 STR (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)011PU0W0(Rn:4)(Rt:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)} {lor(P,lnot(W))}	STR_reg_A1

# A8.8.207 STRB (immediate, ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)010PU1W0(Rn:4)(Rt:4)(imm12:12)	{ne(cond,15)} {lor(P,lnot(W))}	STRB_imm_A1

# A8.8.208 STRB (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)011PU1W0(Rn:4)(Rt:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)} {lor(P,lnot(W))}	STRB_reg_A1

# A8.8.209 STRBT
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0100U110(Rn:4)(Rt:4)(imm12:12)	{ne(cond,15)}	STRBT_A1
# A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0110U110(Rn:4)(Rt:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	STRBT_A2

# A8.8.210 STRD (immediate)
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)000PU1W0(Rn:4)(Rt:4)(imm4H:4)1111(imm4L:4)	{ne(cond,15)} {lor(opcode<24>,lnot(opcode<21>))}	STRD_imm_A1 # Note manual disambiguation (see A5.2)

# A8.8.211 STRD (register)
# A1 ARMv5TE*, ARMv6*, ARMv7
(cond:4)000PU0W0(Rn:4)(Rt:4)(0000)1111(Rm:4)	{ne(cond,15)} {lor(opcode<24>,lnot(opcode<21>))}	STRD_reg_A1 # Note manual disambiguation (see A5.2)

# A8.8.212 STREX
# A1 ARMv6*, ARMv7
(cond:4)00011000(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREX_A1

# A8.8.213 STREXB
# A1 ARMv6K, ARMv7
(cond:4)00011100(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREXB_A1

# A8.8.214 STREXD
# A1 ARMv6K, ARMv7
(cond:4)00011010(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREXD_A1

# A8.8.215 STREXH
# A1 ARMv6K, ARMv7
(cond:4)00011110(Rn:4)(Rd:4)(1111)1001(Rt:4)	{ne(cond,15)}	STREXH_A1

# A8.8.217 STRH (immediate, ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)000PU1W0(Rn:4)(Rt:4)(imm4H:4)1011(imm4L:4)	{ne(cond,15)} {lor(P,lnot(W))}	STRH_imm_A1

# A8.8.218 STRH (register)
# A1 ARMv4*, ARMv5T*, ARMv7
(cond:4)000PU0W0(Rn:4)(Rt:4)(0000)1011(Rm:4)	{ne(cond,15)} {lor(P,lnot(W))}	STRH_reg_A1

# A8.8.219 STRHT
# A1 ARMv6T2, ARMv7
(cond:4)0000U110(Rn:4)(Rt:4)(imm4H:4)1011(imm4L:4)	{ne(cond,15)}	STRHT_A1
# A1 ARMv6T2, ARMv7
(cond:4)0000U010(Rn:4)(Rt:4)(0000)1011(Rm:4)	{ne(cond,15)}	STRHT_A2

# A8.8.220 STRT
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0100U010(Rn:4)(Rt:4)(imm12:12)	{ne(cond,15)}	STRT_A1
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0110U010(Rn:4)(Rt:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	STRT_A2

# A8.8.222 SUB (immediate, ARM)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0010010S(Rn:4)(Rd:4)(imm12:12)	{ne(cond,15)} {lor(ne(Rn,15),S)} {ne(Rn,13)}	SUB_imm_A1 # NOTE: SUBS PC, LR

# A8.8.223 SUB (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000010S(Rn:4)(Rd:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)} {ne(Rn,13)}	SUB_reg_A1 # NOTE: SUBS PC, LR

# A8.8.224 SUB (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000010S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	SUB_rsr_A1

# A8.8.225 SUB (SP minus immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0010010S1101(Rd:4)(imm12:12)	{ne(cond,15)}	SUB_sp_imm_A1 # NOTE: SUBS PC, LR

# A8.8.226 SUB (SP minus register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000010S1101(Rd:4)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	SUB_sp_reg_A1 # NOTE: SUBS PC, LR

# A8.8.228 SVC (previously SWI)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)1111(imm24:24)	{ne(cond,15)}	SVC_A1

# A8.8.229 SWP, SWPB
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00010B00(Rn:4)(Rt:4)(0000)1001(Rt2:4)	{ne(cond,15)}	SWP_SWPB_A1

# A8.8.230 SXTAB
# A1 ARMv6*, ARMv7
(cond:4)01101010(Rn:4)(Rd:4)(rotate:2)(00)0111(Rm:4)	{ne(cond,15)} {ne(Rn,15)}	SXTAB_A1

# A8.8.231 SXTAB16
# A1 ARMv6*, ARMv7
(cond:4)01101000(Rn:4)(Rd:4)(rotate:2)(00)0111(Rm:4)	{ne(cond,15)} {ne(Rn,15)}	SXTAB16_A1

# A8.8.232 SXTAH
# A1 ARMv6*, ARMv7
(cond:4)01101011(Rn:4)(Rd:4)(rotate:2)(00)0111(Rm:4)	{ne(cond,15)} {ne(Rn,15)}	SXTAH_A1

# A8.8.233 SXTB
# A1 ARMv6*, ARMv7
(cond:4)011010101111(Rd:4)(rotate:2)(00)0111(Rm:4)	{ne(cond,15)}	SXTB_A1

# A8.8.234 SXTB16
# A1 ARMv6*, ARMv7
(cond:4)011010001111(Rd:4)(rotate:2)(00)0111(Rm:4)	{ne(cond,15)}	SXTB16_A1

# A8.8.235 SXTH
# A1 ARMv6*, ARMv7
(cond:4)011010111111(Rd:4)(rotate:2)(00)0111(Rm:4)	{ne(cond,15)}	SXTH_A1

# A8.8.237 TEQ (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00110011(Rn:4)(0000)(imm12:12)	{ne(cond,15)}	TEQ_imm_A1

# A8.8.238 TEQ (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00010011(Rn:4)(0000)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	TEQ_reg_A1

# A8.8.239 TEQ (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00010011(Rn:4)(0000)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	TEQ_rsr_A1

# A8.8.240 TST (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00110001(Rn:4)(0000)(imm12:12)	{ne(cond,15)}	TST_imm_A1

# A8.8.241 TST (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00010001(Rn:4)(0000)(imm5:5)(type:2)0(Rm:4)	{ne(cond,15)}	TST_reg_A1

# A8.8.242 TST (register-shifted register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00010001(Rn:4)(0000)(Rs:4)0(type:2)1(Rm:4)	{ne(cond,15)}	TST_rsr_A1

# A8.8.243 UADD16
# A1 ARMv6*, ARMv7
(cond:4)01100101(Rn:4)(Rd:4)(1111)0001(Rm:4)	{ne(cond,15)}	UADD16_A1

# A8.8.244 UADD8
# A1 ARMv6*, ARMv7
(cond:4)01100101(Rn:4)(Rd:4)(1111)1001(Rm:4)	{ne(cond,15)}	UADD8_A1

# A8.8.245 UASX
# A1 ARMv6*, ARMv7
(cond:4)01100101(Rn:4)(Rd:4)(1111)0011(Rm:4)	{ne(cond,15)}	UASX_A1

# A8.8.246 UBFX
# A1 ARMv6T2, ARMv7
(cond:4)0111111(widthm1:5)(Rd:4)(lsb:5)101(Rn:4)	{ne(cond,15)}	UBFX_A1

# A8.8.247 UDF
# A1 ARMv4*, ARMv5T*, ARMv6, ARMv7
111001111111(imm12:12)1111(imm4:4)	UDF_A1

# A8.8.248 UDIV
# A1 ARMv7E, ARMv7opt
(cond:4)01110011(Rd:4)(1111)(Rm:4)0001(Rn:4)	{ne(cond,15)}	UDIV_A1

# A8.8.249 UHADD16
# A1 ARMv6*, ARMv7
(cond:4)01100111(Rn:4)(Rd:4)(1111)0001(Rm:4)	{ne(cond,15)}	UHADD16_A1

# A8.8.250 UHADD8
# A1 ARMv6*, ARMv7
(cond:4)01100111(Rn:4)(Rd:4)(1111)1001(Rm:4)	{ne(cond,15)}	UHADD8_A1

# A8.8.251 UHASX
# A1 ARMv6*, ARMv7
(cond:4)01100111(Rn:4)(Rd:4)(1111)0011(Rm:4)	{ne(cond,15)}	UHASX_A1

# A8.8.252 UHSAX
# A1 ARMv6*, ARMv7
(cond:4)01100111(Rn:4)(Rd:4)(1111)0101(Rm:4)	{ne(cond,15)}	UHSAX_A1

# A8.8.253 UHSUB16
# A1 ARMv6*, ARMv7
(cond:4)01100111(Rn:4)(Rd:4)(1111)0111(Rm:4)	{ne(cond,15)}	UHSUB16_A1

# A8.8.254 UHSUB8
# A1 ARMv6*, ARMv7
(cond:4)01100111(Rn:4)(Rd:4)(1111)1111(Rm:4)	{ne(cond,15)}	UHSUB8_A1

# A8.8.255 UMAAL
# A1 ARMv6*, ARMv7
(cond:4)00000100(RdHi:4)(RdLo:4)(Rm:4)1001(Rn:4)	{ne(cond,15)}	UMAAL_A1

# A8.8.256 UMLAL
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000101S(RdHi:4)(RdLo:4)(Rm:4)1001(Rn:4)	{ne(cond,15)}	UMLAL_A1

# A8.8.257 UMULL
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0000100S(RdHi:4)(RdLo:4)(Rm:4)1001(Rn:4)	{ne(cond,15)}	UMULL_A1

# A8.8.258 UQADD16
# A1 ARMv6*, ARMv7
(cond:4)01100110(Rn:4)(Rd:4)(1111)0001(Rm:4)	{ne(cond,15)}	UQADD16_A1

# A8.8.259 UQADD8
# A1 ARMv6*, ARMv7
(cond:4)01100110(Rn:4)(Rd:4)(1111)1001(Rm:4)	{ne(cond,15)}	UQADD8_A1

# A8.8.260 UQASX
# A1 ARMv6*, ARMv7
(cond:4)01100110(Rn:4)(Rd:4)(1111)0011(Rm:4)	{ne(cond,15)}	UQASX_A1

# A8.8.261 UQSAX
# A1 ARMv6*, ARMv7
(cond:4)01100110(Rn:4)(Rd:4)(1111)0101(Rm:4)	{ne(cond,15)}	UQSAX_A1

# A8.8.262 UQSUB16
# A1 ARMv6*, ARMv7
(cond:4)01100110(Rn:4)(Rd:4)(1111)0111(Rm:4)	{ne(cond,15)}	UQSUB16_A1

# A8.8.263 USQUB8
# A1 ARMv6*, ARMv7
(cond:4)01100110(Rn:4)(Rd:4)(1111)1111(Rm:4)	{ne(cond,15)}	UQSUB8_A1

# A8.8.264 USAD8
# A1 ARMv6*, ARMv7
(cond:4)01111000(Rd:4)1111(Rm:4)0001(Rn:4)	{ne(cond,15)}	USAD8_A1

# A8.8.265 USADA8
# A1 ARMv6*, ARMv7
(cond:4)01111000(Rd:4)(Ra:4)(Rm:4)0001(Rn:4)	{ne(cond,15)} {ne(Ra,15)}	USADA8_A1

# A8.8.266 USAT
# A1 ARMv6*, ARMv7
(cond:4)0110111(sat_imm:5)(Rd:4)(imm5:5)(sh)01(Rn:4)	{ne(cond,15)}	USAT_A1

# A8.8.267 USAT16
# A1 ARMv6*, ARMv7
(cond:4)01101110(sat_imm:4)(Rd:4)(1111)0011(Rn:4)	{ne(cond,15)}	USAT16_A1

# A8.8.268 USAX
# A1 ARMv6*, ARMv7
(cond:4)01100101(Rn:4)(Rd:4)(1111)0101(Rm:4)	{ne(cond,15)}	USAX_A1

# A8.8.269 USUB16
# A1 ARMv6*, ARMv7
(cond:4)01100101(Rn:4)(Rd:4)(1111)0111(Rm:4)	{ne(cond,15)}	USUB16_A1

# A8.8.270 USUB8
# A1 ARMv6*, ARMv7
(cond:4)01100101(Rn:4)(Rd:4)(1111)1111(Rm:4)	{ne(cond,15)}	USUB8_A1

# A8.8.271 UXTAB
# A1 ARMv6*, ARMv7
(cond:4)01101110(Rn:4)(Rd:4)(rotate:2)(00)0111(Rm:4)	{ne(cond,15)} {ne(Rn,15)}	UXTAB_A1

# A8.8.272 UXTAB16
# A1 ARMv6*, ARMv7
(cond:4)01101100(Rn:4)(Rd:4)(rotate:2)(00)0111(Rm:4)	{ne(cond,15)} {ne(Rn,15)}	UXTAB16_A1

# A8.8.273 UXTAH
# A1 ARMv6*, ARMv7
(cond:4)01101111(Rn:4)(Rd:4)(rotate:2)(00)0111(Rm:4)	{ne(cond,15)} {ne(Rn,15)}	UXTAH_A1

# A8.8.274 UXTB
# A1 ARMv6*, ARMv7
(cond:4)011011101111(Rd:4)(rotate:2)(00)0111(Rm:4)	{ne(cond,15)}	UXTB_A1

# A8.8.275 UXTB16
# A1 ARMv6*, ARMv7
(cond:4)011011001111(Rd:4)(rotate:2)(00)0111(Rm:4)	{ne(cond,15)}	UXTB16_A1

# A8.8.276 UXTH
# A1 ARMv6*, ARMv7
(cond:4)011011111111(Rd:4)(rotate:2)(00)0111(Rm:4)	{ne(cond,15)}	UXTH_A1

# A8.8.424 WFE
# A1 ARMv6K, ARMv7
(cond:4)001100100000(11110000)00000010	{ne(cond,15)}	WFE_A1

# A8.8.425 WFI
# A1 ARMv6K, ARMv7
(cond:4)001100100000(11110000)00000011	{ne(cond,15)}	WFI_A1

# A8.8.426 YIELD
# A1 ARMv6K, ARMv7
(cond:4)001100100000(11110000)00000001	{ne(cond,15)}	YIELD_A1

# B9.3.2 CPS (ARM)
# A1 ARMv6*, ARMv7
111100010000(imod:2)M0(0000000)AIF0(mode:5)	CPS_A1

# B9.3.3 ERET
# A1 ARMv7VE
(cond:4)00010110(000000000000)0110(1110)	{ne(cond,15)}	ERET_A1

# B9.3.4 HVC
# A1 ARMv7VE
(cond:4)00010100(imm12:12)0111(imm4:4)	{ne(cond,15)}	HVC_A1

# B9.3.5 LDM (exception return)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)100PU1W1(Rn:4)1(reglist:15)	{ne(cond,15)}	LDM_exception_A1

# B9.3.6 LDM (user registers)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)100PU1(0)1(Rn:4)0(reglist:15)	{ne(cond,15)}	LDM_user_A1

# B9.3.8 MRS (banked register)
# A1 ARMv7VE
(cond:4)00010R00(m1:4)(Rd:4)(00)1m0000(0000)	{ne(cond,15)}	MRS_banked_A1

# B9.3.9 MRS
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00010R00(1111)(Rd:4)(00)0(0)0000(0000)	{ne(cond,15)}	MRS_A1

# B9.3.10 MSR (banked register)
# A1 ARMv7VE
(cond:4)00010R10(m1:4)(111100)1m0000(Rn:4)	{ne(cond,15)}	MSR_banked_A1

# B9.3.11 MSR (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00110R10(mask:4)(1111)(imm12:12)	{ne(cond,15)}	{lor(mask,R)}	MSR_imm_A1

# B9.3.12 MSR (register)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)00010R10(mask:4)(111100)0(0)0000(Rn:4)	{ne(cond,15)}	MSR_reg_A1

# B9.3.13 RFE
# A1 ARMv6*, ARMv7
1111100PU0W1(Rn:4)(0000101000000000)	RFE_A1

# B9.3.14 SMC (previously SMI)
# A1 SecExt
(cond:4)00010110(000000000000)0111(imm4:4)	{ne(cond,15)}	SMC_A1

# B9.3.16 SRS (ARM)
# A1 ARMv6*, ARMv7
1111100PU1W0(110100000101000)(mode:5)	SRS_A1

# B9.3.17 STM (user registers)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)100PU1(0)0(Rn:4)(reglist:16)	{ne(cond,15)}	STM_user_A1
