! ###############################################################
! ###############################################################
! ###                                                         ###
! ###  IOMD system level block models                         ###
! ###                                                         ###
! ###  Created 18/8/92: David Flynn                           ###
! ###                                                         ###
! ###  IORCLKGEN -  reference & IO clock generator            ###
! ###                                                         ###
! ###############################################################
! ###############################################################
! ###  Revision History:                                      ###
! ###   07/9/92: DWF : RCLKGEN spilt from IOMDSYS file        ###
! ###   15/9/92: DWF : IO clocks and new synchronous RCLK merge #
! ###  11/11/92: DWF : Reset synchroniser added here          ###
! ###  26/11/92: DWF : Reset synchronisation with RCLK fixed  ###
! ###  27/11/92: DWF : Nreset output added                    ###
! ###  03/12/92: DWF : reset async clear (synch back edge)    ###
! ###  17/12/92: DWF : force RCLK during reset                ###
! ###  21/12/92: DWF : invert RCLK unsync inputs for speedup  ###
! ###                  noddy invertors added for simplicity   ###
!      14/1/93   WHO   moved mclk gen to here                 ###
!      20/1/93   WHO   inverted sense of busrq for speed      ###
!       2/3/93   WHO   had to force reset on por for vectors  ###
! ###############################################################

FROM iomd.rclksm           IMPORT  rclksm
FROM STDParts.Misc         IMPORT $Sink,$SDTFF
FROM STDParts.Gates        IMPORT $SGate1,$SGate2,$SGate3


! ###############################################################
! IOMD RCLKGEN (default RCLK statemachine)
! ###############################################################

BLOCK RCLKGEN(
  {IN}  ck32,
  {IN}  Ninit,
  {IN}  defrclk,
  {IN}  rclkramUN,
  {IN}  rclkromUN,
  {IN}  rclkprogUN,
  {IN}  Nresetin,
  {IN}  mclken,
  {IN}  iomclkl,
  {IN}  casdel,
  {IN}  Nbusrq,
  {IN}  por,
  {OUT} reset,
  {OUT} Nreset,
  {OUT} clk8,
  {OUT} clk16,
  {OUT} rclk,
  {OUT} mclk
)

npor = $SGate1(por) => Npor WITH (delay=ns_1,OP=INV)

defrclk1 = $SGate2(defrclk,reset) => defrclk1 WITH (OP=OR, delay=ns_3)

rclkrambg = $SGate2(casdel, Nbusrq) => Nrclkramwe WITH (op=NAND, delay=ns_2)
rclkramUS = $SGate2(rclkramUN, Nrclkramwe) => rclkramUS WITH (OP=NAND, delay=2)
rclkromUS = $SGate1(rclkromUN) => rclkromUS WITH (OP=INV, delay=1)
rclkprogUS = $SGate1(rclkprogUN) => rclkprogUS WITH (OP=INV, delay=1)

! ###############################################################
! MCLK generation

  mclk1  = $SGate2(rclk, mclken) => mclk1
                   WITH (op=AND, delay=ns_2)
  mclk   = $SGate2(mclk1, iomclkl) => mclk
                   WITH (op=OR, delay=ns_2)

rclksm = rclksm(
     ck32,
     Ninit,
     defrclk1,
     rclkramUS,
     rclkromUS,
     rclkprogUS
   )
   =>  (
     clk8,
     clk16,
     rclk
   )

   Nck32 = $SGate1(ck32) => Nck32 WITH (delay=ns_1,OP=INV)

   res1 = $SDTFF(Nck32,Nresetin,Vdd,Npor) => (Nres1,res1) WITH (delay=ns_4)
   res2 = $SDTFF(Nck32,Nres1b,Vdd,Npor)   => (Nres2,res2) WITH (delay=ns_4)

   snk = $Sink(qbar(res1,res2))

   reset = $SGate1(Nres2) => reset WITH (OP=INV, delay=ns_3)
   Nreset = $SGate1(res2) => Nreset WITH (OP=INV, delay=ns_3)

! force reset hold until RCLK is in low phase
   Nres1a = $SGate3(Nres1,rclk,res2) => Nres1a WITH (OP=NAND, delay=ns_3)
   Nres1b = $SGate2(Nres1,Nres1a) => Nres1b WITH (OP=AND, delay=ns_3)

END {RCLKGEN}  
