!13 13 16
!#vti pla code/lg to asim sidpla convertor <ram>
!# 13 inputs, 13 outputs, 16 terms
!#
!#VTI STATE MACHINE
!###############################################################
!###############################################################
!###                                                         ###
!###  IOMD RAMSM : RAMCTL STATE MACHINE                      ###
!###                                                         ###
!###  Created 10/9/92: David Flynn                           ###
!###                                                         ###
!###                                                         ###
!###############################################################
!###############################################################
!###  Revision History:                                      ###
!###   11/9/92: DWF : completely reworked                    ###
!###   18/1/93: AS  : AND rburst and wburst with             ###
!###                  (dmagoing OR busrq)                    ###
!###                  AND ramgo with busrq                   ###
!###    1/3/93: WHO : added stateM -> stateSB video speedup  ###
!###############################################################
!sm ramsm;
!clock clk32 32;
!
!reset init --> stateI;
!
!inputs
!# from bus state machine
!         ramgo
!         dmagoing      
!         busrq
!# from ramglue
!         wait
!         rburst
!         wburst
!         ;
!
!outputs
!         out[5:0]
!         ;
!
!
!# these are the carefully encoded state outputs
!
!define ramstate
!  I      = 000000
!  SB     = 100010
!  SR     = 110000
!   R     = 010000
!  SRM    = 111000
!   RMCB  = 011110
!    M    = 001000
!   RM    = 011000
!   RMDB  = 011011
!   RMB   = 011010
!  ;
!
!
!# initial state - no active outputs, RAM precharged
!state stateI=000000
!    dmagoing --> stateSB out=SB,
!    ramgo & busrq--> stateR out=R,
!    --> stateI out=I;
!
!# State bit and Bus Clock (for DMA dummy RCLK)
!state stateSB=100010
!    --> stateSR out=SR;
!
!# State bit and RAS (for DMA Refresh and VCTL cycle stretching)
!state stateSR=110000
!    !wait --> stateSRM out=SRM,
!    --> stateSR out=SR;
!
!# RAS asserted (ARM cycles)
!state stateR=010000
!    --> stateSRM out=SRM;
!
!# State bit, RAS and colMux
!state stateSRM=111000
!    --> stateRMCB out=RMCB;
!
!# RAS, colMux, CAS and Busclk
!state stateRMCB=011110
!    rburst & (dmagoing | busrq) --> stateSRM out=SRM,
!    wburst & (dmagoing | busrq)--> stateRM out=RM,
!    --> stateM out=M;
!
!# RAS and colMux
!state stateRM=011000
!    --> stateRMDB out=RMDB;
!
!# RAS, colMux, DelayedCAS and Busclk
!state stateRMDB=011011
!    wburst & (dmagoing | busrq)--> stateRM out=RM,
!    --> stateRMB out=RMB;
!
!# RAS, colMux and Busclk (stretch last write of burst for hold time)
!state stateRMB=011010
!    --> stateM out=M;
!
!# colMux - the first RAS precharge state
!state stateM=001000
!    dmagoing --> stateSB out=SB,        # this is the video speedup
!    --> stateI out=I;
!
!end
!!##cell2 * ram lg * 110 any 0 v8r3_8
!## "18-Jan-93 GMT" "17:58:08 GMT" "18-Jan-93 GMT" "17:58:08 GMT" astevens * _
!#Assign these values to the symbols:
!#000000 : i
!#100010 : sb
!#110000 : sr
!#010000 : r
!#111000 : srm
!#011110 : rmcb
!#001000 : m
!#011000 : rm
!#011011 : rmdb
!#011010 : rmb
!#Assign these values to the symbols:
!#000000 : statei
!#100010 : statesb
!#010000 : stater
!#110000 : statesr
!#111000 : statesrm
!#011110 : statermcb
!#011000 : staterm
!#001000 : statem
!#011011 : statermdb
!#011010 : statermb
!#Outputs not computed by the PLA:
!#Inputs not used by the PLA:
!#clk32
!#Inputs to the pla, from the left:
!--------------|---------------
!        d     | ssssss        
!        m     | mmmmmm        
!ssssss  a  rw | ______        
!mmmmmm rgb bb | ssssss        
!______ aouwuu | rrrrrr        
!ssssss misarr | 654321 o      
!rrrrrr gnriss | ______ u      
!654321 ogqttt | dddddd t      
!--------------|---------------
!              |        543210 
!--------------|-++++++-++++++-
!1x1xxx xxxxxx | 011110 011110 
!xxxxx1 xxxxx0 | 000010 000010 
!011x0x xxxxxx | 010011 010011 
!xxxxx1 xxxxxx | 010000 010000 
!xxxxx1 x00xxx | 000010 000010 
!xxx1xx x1xx1x | 110000 110000 
!xxx1xx xx1x1x | 110000 110000 
!x0xx1x xxxxxx | 110000 110000 
!x10xxx xxxxxx | 110000 110000 
!1xxx0x xxx0xx | 001000 001000 
!xxx1xx x1xxx1 | 010000 010000 
!xxx1xx xx1xx1 | 010000 010000 
!001000 x1xxxx | 100010 100010
!xxxxxx xxxxxx | 000000 000000 
!x00x0x x1xxxx | 100010 100010 
!01xxxx xxxxxx | 001000 001000 
!xx0xxx 101xxx | 010000 010000 
!--------------|---------------
!#SIDLE PROTOTYPE

 FROM STDParts.PLAs  IMPORT $PLA
 FROM STDParts.Misc  IMPORT $Sink,$BDTFF


 BLOCK ramsm(
     ck,
     Ninit,
     ramgo,
     dmagoing,
     busrq,
     wait,
     rburst,
     wburst
   )
   =>  (
     out[5:0],
     Ssm_sr5_d  ! rclk unsynchronised
   )

   soutsnk = $SINK(Sout[5:0])
 
   pla = $PLA(Vdd,Vdd,
     in(
     sm_sr1,
     sm_sr2,
     sm_sr3,
     sm_sr4,
     sm_sr5,
     sm_sr6,
     ramgo,
     dmagoing,
     busrq,
     wait,
     rburst,
     wburst
    )
   )
   =>  plaout(
     Ssm_sr1_d,
     Ssm_sr2_d,
     Ssm_sr3_d,
     Ssm_sr4_d,
     Ssm_sr5_d,
     Ssm_sr6_d,
     Sout[5:0]
   )
   WITH (delay=ns_5,filename=iomd/sid/ramsm)
 
   reg = $BDTFF(
    ck,
     d(
       Ssm_sr1_d,
       Ssm_sr2_d,
       Ssm_sr3_d,
       Ssm_sr4_d,
       Ssm_sr5_d,
       Ssm_sr6_d,
       Sout[5:0]
     ),
     Vdd,Ninit)
   =>  (q(
     sm_sr1,
     sm_sr2,
     sm_sr3,
     sm_sr4,
     sm_sr5,
     sm_sr6,
     out[5:0]
   ),_qbar[11:0])
   WITH (delay=ns_5, edge=+ve)
 
   snk = $Sink(_qbar[11:0])
 
 END {ramsm}
 

