! ###############################################################
! ###############################################################
! ###                                                         ###
! ###  IOMD core level model                                  ###
! ###                                                         ###
! ###  Created 12/8/92: David Flynn                           ###
! ###                                                         ###
! ###   Dummy contents!!                                      ###
! ###                                                         ###
! ###############################################################
! ###############################################################
! ###  Revision History:                                      ###
! ###   12/8/92: DWF :                                        ###
! ###   19/8/92: DWF : remove seq                             ###
! ###   25/8/92: DWF : SPEC E. signal changes                 ###
! ###   28/8/92: SAS : Addition of VCTL                       ###
! ###   01/9/92: DWF : Addition of DBUS, DBE tied off high    ###
! ###                : tie off VBUSAK=VDD temporarily         ###
! ###   02/9/92: DWF : Removed Nreset from BUSCTL             ###
! ###   07/9/92: AS  : Moved ramcr & vrefcr to RAMCTL         ###
! ###   14/9/92: AS  : Addition of mouse block                ###
! ###   15/9/92: DF  : New synchronised rclk strategy (RCLKGEN) #
! ###   15/9/92: WHO : Added dag block                        ###
! ###   15/9/92: WHO : removed Npor from sdnen and viden      ###
! ###   16/9/92: DWF : 2nd processor interface added to IOMD  ###
! ###   16/9/92: DF  : armrq renamed busrq with 2nd proc added ##
! ###   16/9/92: AS  : Change bus to data[] from iod[] & d[]  ###
! ###   18/9/92: WHO : added iodir[] from dag                 ###
! ###   21/9/92: WHO : added sndir[] form dag to SOUND        ###
! ###   22/9/92  WHO   moved dmastart to ramctl               ###
! ###   25/9/92: AS  : Added testbus output from ADEC         ###
! ###   07/10/92: AS : Added rclk output                      ###
! ###   13/10/92 WHO : Added rclk to DBUS for bug fix         ###
! ###   20/10/92 AS  : Temporarily connected dagint to irq    ###
! ###   29/10/92 WHO : Added KBD block                        ###
! ###    3/11/92 WHO : wired testbus[10:8] to kbd test inputs ###
! ###    4/11/92 AS  : dmach[2:0] now goes to dbus            ###
! ###    5/11/92 SAS : Added IOINT                            ###
! ###   11/12/92 DF  : removed IOGOING signal                 ###
! ###   15/12/92 WO  : removed soundreg, vram form adec       ###
! ###                  removed Nirqin and unused testbus bits ###
! ###                  tidied up generally                    ###
! ###   21/12/92 DF  : RCLK sources all inverted              ###
! ###   23/12/92 DF  : RCLK sources all inverted              ###
!       14/1/93  WO    moved mclk gen to rclkgen              ###
!       20/1/93  WO    changed busrq to Nbusrq for speed in nl ##
!        1/2/93  WO    removed rclk from dag                   ##
!        2/2/93  WO    added por to rclkgen                    ##
! ###############################################################

FROM StdParts.Misc         IMPORT  $Sink, $StoB, $SDTFF
FROM StdParts.Gates        IMPORT  $SGate1, $SGate2

FROM iomd.adec             IMPORT  ADEC
FROM iomd.amux             IMPORT  AMUX
FROM iomd.busctl           IMPORT  BUSCTL
FROM iomd.dag              IMPORT  DAG
FROM iomd.dbus             IMPORT  DBUS
FROM iomd.funnel           IMPORT  FUNNEL
FROM iomd.ioctl            IMPORT  IOCTL
FROM iomd.ioint            IMPORT  IOINT
FROM iomd.kbd              IMPORT  KBD
FROM iomd.progctl          IMPORT  PROGCTL
FROM iomd.ramctl           IMPORT  RAMCTL
FROM iomd.rclkgen          IMPORT  RCLKGEN
FROM iomd.romctl           IMPORT  ROMCTL
FROM iomd.vctl             IMPORT  VCTL
FROM iomd.mouse            IMPORT  MOUSE

! ###############################################################
! dummy tie offs:

BLOCK SNK({IN} s)
  sink = $Sink(z(s, s))
END {SNK}

BLOCK TBDHI({OUT} s)
  tbdhi = $SGate1(Vdd) => s WITH (delay=1, OP=BUFF)
END {TBDHI}

BLOCK TBDLO({OUT} s)
  tbdlo = $SGate1(Vss) => s WITH (delay=1, OP=BUFF)
END {TBDLO}



! ###############################################################
! IOMD core interface
! ###############################################################

BLOCK IOMDcore(
! system signals
  {IN}  clk64,
  {IN}  por,
  {OUT} NenNreset,
  {OUT} Nresetout,
  {IN}  Nresetin,
  {OUT} forceHiZ,
! ARM600 interface
  {OUT} mclk,
  {IN}  Nmreq,
  {IN}  Npreq,
  {OUT} rclk,
  {IN}  a[28:0],
  {OUT} Nendoutlo,
  {OUT} Nendouthi,
  {IN}  din[31:0],
  {OUT} dout[31:0],
  {IN}  Nrw,
  {IN}  Nbw,
  {OUT} dbe,
  {OUT} Nfiq,
  {IN}  Nfiqin,
  {OUT} Nirq,
! DRAM/VRAM Interface
  {OUT} ra[11:0],
  {IN}  Nfcas[3:0],
  {OUT} Nras[3:0],
  {OUT} Nvras,
  {OUT} Ncas[3:0],
  {OUT} Nwe[1:0],
  {OUT} Ndt[1:0],
  {OUT} sc,
  {OUT} Nse,
  {OUT} Ncdoe,
  {OUT}  dsf,
! VIDC20 interface
  {OUT} pclk,
  {IN}  qsf,
  {IN}  Nvidrq,
  {IN}  vnc,
  {IN}  flybk,
  {OUT} Nvidak,
  {OUT} Nprog,
  {IN}  Nsndrq,
  {OUT} Nsndak,
! system decodes
  {OUT} Nromcs,
! IO :: interface
  {OUT} clk16,
  {OUT} Neasis,
  {IN}  ready,
  {OUT} ref8m,
  {OUT} Niorq,
  {IN}  Niogt,
  {OUT} Nms,
  {OUT} Nenbd,
  {OUT} bdout[15:0],
  {IN}  bdin[15:0],
! IO DMA
  {IN}  drq[3:0],
  {OUT} Ndack[3:0],
  {OUT} tc,
! IO :: buffer/latch control
  {OUT} Nwbe,
  {OUT} Nrbe,
  {OUT} Nblw,
  {OUT} Nblr,
  {IN}  Nbl,
! IO :: handshake signals
  {OUT} clk2,
  {OUT} Nior,
  {OUT} Niow,
  {OUT} Npboe,
  {OUT} Nccs,
  {OUT} Ncdack,
  {OUT} Nsccs,
  {OUT} Nsio,
  {OUT} lrnw,
! IO :: interrupt inputs
  {IN}  Npfiq,
  {IN}  Npirq,
  {IN}  Nsintr,
  {IN}  Nscirq,
  {IN}  Nfintr,
  {IN}  Nindex,
  {IN}  fdrq,
  {IN}  pintr,
  {IN}  Niext,
! IO :: control I/Os
  {OUT} Nenid,
  {OUT} idout,
  {IN}  idin,
  {OUT} Neniicc,
  {OUT} iiccout,
  {IN}  iiccin,
  {OUT} Neniicd,
  {OUT} iicdout,
  {IN}  iicdin,
! IO :: keyboard
  {OUT} Nenkclk,
  {OUT} kclkout,
  {IN}  kclkin,
  {OUT} Nenkdata,
  {OUT} kdataout,
  {IN}  kdatain,
! IO :: mouse
  {IN}  msx[1:0],
  {IN}  msy[1:0],
! AD1848 sound codec interface
  {IN}  cdrq,
  {IN}  pdrq,
  {OUT} Nsndcs,
  {OUT} Nscdack,
  {OUT} Nspdack
)

! ###############################################################
! this output goes to the tristate enable of all output-only pads

t003 = TBDLO(forceHiZ)

! ###############################################################
! open-drain outputs

od1  = TBDLO(kclkout)
od2  = TBDLO(kdataout)
od3  = TBDLO(idout)
od4  = TBDLO(iiccout)
od5  = TBDLO(iicdout)

! ###############################################################

adec = ADEC(
! system signals
  {IN}  mclk,
  {IN}  reset,
! decode address range
  {IN}  a[28:12],
  {IN}  a[8:2],
  {IN}  Nrw,
! external VIDC write strobe
  {IN}  prog,
! major decodes
  {OUT} romdec,
  {OUT} ramdec,
  {OUT} io32dec,
  {OUT} iodec,
  {OUT} progdec,
  {OUT} extprog,
  {OUT} vprog,
  {OUT} iomddec,
! external strobe
  {OUT} Nprog,
! external decodes
  {OUT} iointreg,
  {OUT} mousereg,
  {OUT} ioctlreg,
  {OUT} ramreg,
  {OUT} dagreg,
  {OUT} fsizewt,
  {OUT} lwrite,
  {OUT} la[7:2],
  {OUT} lah[27:12],
! control signals (register controlled)
  {IO}  data[7:0],
  {OUT} romc[4:0],
  {OUT} burst,
  {OUT} fsize[7:0],
  {OUT} testbuss[1:0], ! strobed test bits
  {OUT} testbusc[11:8] ! constant test bits
)

! Document here what the various testbus bits do...
! N.B. testbus[7:0] are strobes (one-time only), and testbus[23:8] are flags
! testbuss[0] = refresh counter reset control
! testbuss[1] = IOINT Test clock
! testbusc[8] = keyboard test1 input (speeds kbd i/f up by 128)
! testbusc[9] = keyboard test2 input (reduces timeout by factor of 8)
! testbusc[10] = keyboard test3 input (gates t16 to rxpar in status)
! testbusc[11] = IOINT clock multiplexor control
! All other bits unused

! ###############################################################

amux = AMUX(
  {IN}  ramc[2:0],
  {IN}  a[25:2],
  {IN}  da[25:2],
  {IN}  rclk,
  {IN}  cas,
  {IN}  dmagoing,
  {IN}  colmux,
  {IN}  fcolmux,
  {OUT} count0,
  {OUT} ra[11:0],
  {OUT} four,
  {OUT} eight,
  {OUT} maxseq
)


! ###############################################################

busctl = BUSCTL(
! clock signals
  {IN}  rclk,
  {IN}  mclk,
! arm request
  {IN}  Nmreq,
  {IN}  Npreq,
  {OUT} Nbusrq,
! state machine inputs
  {IN}  NenNreset, !! post review change:: was Ninit, !init for test sync
  {IN}  Nreset,
  {IN}  romdec,
  {IN}  ramdec,
  {IN}  iodec,
  {IN}  progdec,
  {IN}  la[3:2],
  {IN}  Niogti,
  {IN}  eight,
  {IN}  maxseq,
  {IN}  burst,
! DMA request inputs
  {IN}  curdrq,
  {IN}  vsnddrq,
  {IN}  snd0drq,
  {IN}  trandrq,
  {IN}  snd1drq,
  {IN}  refrq,
  {IN}  iodrq,
  {IN}  dmadone,
  {IN}  snd0cod=sndir[0],
! outputs
  {OUT} dmagoing,
  {OUT} dmach[2:0],
  {OUT} Niorqi,
  {OUT} defrclk,
  {OUT} romgo,
  {OUT} ramgo,
  {OUT} proggo,
  {OUT} dmarq,
  {OUT} dmavbus, ! vidrq, sndrq
  {OUT} mclken,
  {OUT} iomclkl
  )

! ###############################################################

dag = DAG(
  {IN}  dmastart,    ! from RAMCTL off clk32
  {IN}  la[7:2],     ! from ADEC
  {IN}  reset,       ! from IOINT
  {IN}  lwrite,      ! from PROGCTL
  {IN}  prog,        ! from ADEC
  {IN}  dagreg,      ! from VCTL
  {IN}  flybid,       ! from VCTL
  {IN}  vncd,        ! from VCTL
  {IN}  dmagoing,    ! from BUSCTL
  {IN}  dmach[2:0],  ! from BUSCTL
  {IN}  ioch[1:0],   ! from IOCTL
  {IN}  ramdmaend,   ! from RAMCTL
  {OUT} da[28:0],    ! to AMUX and RAMCTL
  {OUT} dsize[1:0],  ! to RAMCTL
  {OUT} dwrite,      ! to RAMCTL
  {OUT} dagint,      ! to IOINT
  {OUT} snden[1:0],  ! bit 0 to SOUND
  {OUT} sndir[1:0],  ! to SOUND
  {OUT} vsnden,      ! to BUSCTL
  {OUT} viden,       ! to VCTL
  {OUT} ioden[3:0],  ! to IOCTL
  {OUT} iodir[3:0],  ! to IOCTL
  {OUT} dag_tc[3:0], ! to IOCTL
  {OUT} vrm,         ! to VCTL
  {BID} data[31:0]   ! system bus
)

! ###############################################################

dbus = DBUS(
  {IN}  rclk,
  {IN}  iomddec,   ! from ADEC
  {IN}  iodec,     ! from ADEC
  {IN}  io32dec,   ! from ADEC
  {IN}  lwrite,    ! from ADEC
  {IN}  dmagoing,  ! from BUSCTL
  {IN}  dwrite,    ! from DAG
  {IN}  dmach[2:0],! from BUSCTL
  {IN}  dsize[1:0],! from DAG
  {IN}  din[31:0], ! from PADS
  {IO}  data[31:0],! to <all over>
  {OUT} dout[31:0],! to PADS
  {OUT} Nendoutlo, ! to PADS
  {OUT} Nendouthi,
  {OUT} dbe
)

! ###############################################################

funnel = FUNNEL(data[31:0], bdin[15:0], fwt_lat[3:0], fwt_s[1:0], Nfrd[3:0], frd_oe, frd_bh, Nbl, Nmemc, sound)
       => (bdout[15:0], Nblr)

! ###############################################################

ioctl = IOCTL(da[1:0], dag_tc[3:0], data[7:0], dmach[2:0], drq[3:0], dsize[1:0], ioden[3:0], iodir[3:0],
         la[3:2], lah[27:12], Nfcas[3:0], snden[1:0], cas, cdrq, clk16, dmagoing, ioctlreg, iodec, io32dec,
         lwrite, Ninit, Niogt, Niorqi, pdrq, prog, rclk, ready, ref8m, reset, sndir[1])
      => (Ndack[3:0], Nfrd[3:0], fwt_lat[3:0], fwt_s[1:0], ioch[1:0], clk2, frd_oe, frd_bh, iodrq, lrnw, 
          Nblw, Nccs, Ncdack, Neasis, Nenbdi, Nior, Niogti, Niorq, Niow, Nmemc, Nms, Npboe, Nrbe, Nsccs, Nsio,
          Nscdack, Nsndcs, Nspdack, Nwbe, sound, snd0drq, snd1drq, tc)

! Bodge to stop bus clashes - no need to implement this
! Nenbdi connects to Nenbd in real life
  enbdid = $SDTFF(clk32, Nenbdi, Vdd, Vdd) => (Nenbdid, enbdid)
  WITH (delay=ns_3)
  enbdig = $SGate2(Nenbdi, Nenbdid) => Nenbd WITH (op=OR, delay=ns_2)
  enbdsnk = SNK(enbdid)


! ###############################################################

  ioint = IOINT(data[7:0], la[6:2], clk2, clk32, dagint, fdrq, flybi, iiccin, iicdin, idin, iointreg, kbrx,
          kbtx, lwrite, Nfintr, Nfiqin, Niext, Nindex, Npfiq, Npirq, Nscirq, Nsintr, pintr, por, prog, rclk,
          ref8m, reset, testbuss[1], testbusc[11])
      => (kcon_rd, kcon_wt, kdata_rd, kdata_wt, Neniicc, Neniicd, Nenid, Nfiq, Ninitu, Nirq)

! ###############################################################

  kbd = KBD(
 {IN} testbusc[10:8],
 {IN} reset,
 {IN} ref8m,
 {IN} kclkin,
 {IN} kdatain,
 {IN} kcon_rd,
 {IN} kcon_wt,
 {IN} kdata_rd,
 {IN} kdata_wt,
 {IO} data[7:0],
 {OUT} Nenkclk,
 {OUT} Nenkdata,
 {OUT} kbtx,
 {OUT} kbrx)

! ###############################################################

  mouse = MOUSE(
 {IN} rclk,
 {IN} msx[1:0],
 {IN} msy[1:0],
 {IN} mousereg,
 {IN} lwrite,
 {IN} prog,
 {IN} la[2],
 {IO} data[15:0])

! ###############################################################

progctl = PROGCTL(
  {IN}  clk32,
  {IN}  Nreset,
  {IN}  Nbusrq,
  {IN}  dmarq,
  {IN}  proggo,
  {IN}  extprog,
  {IN}  vprog,
  {IN}  vbusak,
  {IN}  la[3:2],
  {IN}  lwrite,
  {OUT} vbusrqprog,   !vbusrq
  {OUT} prog,
  {OUT} rclkprogUN
)

! ###############################################################

ramctl = RAMCTL(
  {IN}  rclk,
  {IN}  clk32,
  {IN}  Nreset,
  {IN}  Nbusrq,
  {IN}  dmarq,
  {IN}  dmavbus,
  {IN}  ramgo,
  {IN}  four,
  {IN}  eight,
  {IN}  maxseq,
  {IN}  dmagoing,
  {IN}  da[28:26],
  {IN}  da[2:0],
  {IN}  a[28:26], 
  {IN}  a[2:0],
  {IN}  count0,
  {IN}  ramreg,
  {IN}  prog,
  {IN}  la[2],
  {IN}  dwrite,
  {IN}  lwrite,
  {IN}  dsize[1:0],
  {IN}  Nbw,
  {IN}  dmach[2:0],
  {IN}  split,
  {IN}  vbusak,
  {IN}  refcres=testbuss[0], {Refresh counter reset test input, from ADEC}
  {OUT} cas,
  {OUT} casdel,
  {OUT} dmastart,
  {OUT} vbusrqram,
  {OUT} rclkramUN,  
  {OUT} colmux,
  {OUT} fcolmux,
  {OUT} Ncas[3:0],
  {OUT} Nras[3:0],
  {OUT} Nvras,
  {OUT} Nwe[1:0],
  {OUT} Ndt[1:0],
  {OUT} dsf,
  {OUT} refrq,
  {OUT} dmadone,
  {OUT} ramdmaend,
  {OUT} ramc[2:0],
  {IO}  data[7:0]
)

! ###############################################################

rclkgen = RCLKGEN(
  {IN}  clk32,
  {IN}  Ninit,   !special init later on
  {IN}  defrclk,
  {IN}  rclkramUN,
  {IN}  rclkromUN,
  {IN}  rclkprogUN,
  {IN}  Nresetin,
  {IN}  mclken,
  {IN}  iomclkl,
  {IN}  casdel,
  {IN}  Nbusrq,
  {IN}  por,
  {OUT} reset,
  {OUT} Nreset,
  {OUT} ref8m,
  {OUT} clk16,
  {OUT} rclk,
  {OUT} mclk
)

! ###############################################################

romctl = ROMCTL(
  {IN}  clk32,
  {IN}  Nreset,
  {IN}  romgo,
  {IN}  Nbusrq,
  {IN}  dmarq,
  {IN}  la[3:2],
  {IN}  romc[4:0],
  {OUT} rclkromUN,
  {OUT} Nromcs
)

! ##############################################################

vctl = VCTL(dmach[2:0],fsize[7:0],clk64,dmagoing,dmavbus,flybk,fsizewt,Ninitu,Nsndrq,Nvidrq,
           qsf,rclk, reset, vrm, vsnden, vbusrqram, vbusrqprog, viden,vnc)
         =>(clk32,curdrq,flybi,flybid,Ncdoe,Ninit,Nse,Nsndak,Nvidak,pclk,sc,vsnddrq,split,trandrq,
            vbusak,vncd)

! ##############################################################

 RSToe = $SGate1(por) => NenNreset WITH (delay=ns_2, OP=INV)

 RSTop = $SGate1(Vss) => Nresetout WITH (delay=ns_2, OP=BUFF)

END {IOMDcore}
