{---------------------------------------------------------------}
{ iodag -  a single io dag block (incrementer is external)      }
{---------------------------------------------------------------}
{ Rev 0.1 Bill Oldfield  14/9/92                                }
{---------------------------------------------------------------}

FROM iomd.dagblks      IMPORT $DAGBSMC
FROM StdParts.TriDrive IMPORT $BBuff
FROM StdParts.Misc     IMPORT $SLatch,$BLatch
FROM StdParts.Gates    IMPORT $SGate1,$SGate2,$SGate3,$SGate4

BLOCK iodag(
    {IN}  prog,         ! the strobe signal that times processor reads and writes
    {IN}  this_io,      ! la[7:5] == this particular io channel
    {IN}  cur_a,        ! la[4:2] == 0
    {IN}  end_a,        ! la[4:2] == 1
    {IN}  cur_b,        ! la[4:2] == 2
    {IN}  end_b,        ! la[4:2] == 3
    {IN}  con,          ! la[4:2] == 4
    {IN}  sta,          ! la[4:2] == 5
    {IN}  lwrite,       ! the processor write qualifier
    {IN}  curin[28:0],  ! the input bus to the current registers
    {IN}  dmago,        ! dmagoing for this particular io channel
    {IN}  ramdmaend,    ! the signal that marks the end of a ram dma
    {IN}  reset) => (   ! master reset
    {OUT} dir,          ! direction bit for export
    {OUT} da[28:0],
    {OUT} ib[4:0],      ! the increment bus
    {OUT} endbus[11:0], ! the end bus
    {BID} d[31:0]
  )

in1 = $SGate1(lwrite) => Nlwrite WITH (delay=ns_2,OP=INV)

or1 = $SGate2(ramdmaend,prog)            => sm_clk    WITH (delay=ns_2,OP=OR)
an1 = $SGate3(this_io,con,lwrite)        => con_addr  WITH (delay=ns_2,OP=AND)
an2 = $SGate2(con_addr,d[7])             => clr_addr  WITH (delay=ns_3,OP=AND)
an3 = $SGate3(this_io,end_a,lwrite)      => enda_addr WITH (delay=ns_3,OP=AND)
an4 = $SGate3(this_io,end_b,lwrite)      => endb_addr WITH (delay=ns_3,OP=AND)

an5  = $SGate4(this_io,cur_a, lwrite,prog) => wr_cura  WITH (delay=ns_3,OP=AND)
nd6  = $SGate4(this_io,cur_a,Nlwrite,prog) => Noe_cura WITH (delay=ns_3,OP=AND)   ! OR dmago && anb
an7  = $SGate2(enda_addr,prog)             => wr_enda  WITH (delay=ns_3,OP=AND)
nd8  = $SGate4(this_io,end_a,Nlwrite,prog) => Noe_enda WITH (delay=ns_3,OP=AND)   ! OR dmago && anb
an9  = $SGate4(this_io,cur_b, lwrite,prog) => wr_curb  WITH (delay=ns_3,OP=AND)
nd10 = $SGate4(this_io,cur_b,Nlwrite,prog) => Noe_curb WITH (delay=ns_3,OP=AND)   ! OR dmago && !anb
an11 = $SGate2(endb_addr,prog)             => wr_endb  WITH (delay=ns_3,OP=AND)
nd12 = $SGate4(this_io,end_b,Nlwrite,prog) => Noe_endb WITH (delay=ns_3,OP=AND)   ! OR dmago && !anb
an12 = $SGate2(con_addr,prog)              => wr_con   WITH (delay=ns_3,OP=AND)
nd14 = $SGate4(this_io,  sta,Nlwrite,prog) => Noe_sta  WITH (delay=ns_3,OP=AND)

bussm = $DAGBSMC(sm_clk,reset,clr_addr,enda_addr,endb_addr,dmago,lasta,lastb,stopa,stopb,enable) => state(ov,int,anb)

cur_a  = $BLatch(wr_cura,Noe_cura,curin[28:0]) => da[28:0] WITH (delay=ns_5)
cur_b  = $BLatch(wr_curb,Noe_curb,curin[28:0]) => da[28:0] WITH (delay=ns_5)

end_a  = $BLatch(wr_enda,Noe_enda,d[11:0]) => endbus[11:0] WITH (delay=ns_5)
end_as = $SLatch(wr_enda,           d[31]) => stopa        WITH (delay=ns_5)
end_al = $SLatch(wr_enda,           d[30]) => lasta        WITH (delay=ns_5)

end_b  = $BLatch(wr_endb,Noe_endb,d[11:0]) => endbus[11:0] WITH (delay=ns_5)
end_bs = $SLatch(wr_endb,           d[31]) => stopb        WITH (delay=ns_5)
end_bl = $SLatch(wr_endb,           d[30]) => lastb        WITH (delay=ns_5)

con_lat = $BLatch(wr_con,     Vss,d[6:0])  => control(dir,enable,ib[4:0]) WITH (delay=ns_5)

sta_buf = $BBuff(state2(ov,int,anb),Noe_sta) => d[2:0] WITH (delay=ns_3)

END {iodag}

