!17 11 41
!#vti pla code/lg to asim sidpla convertor <bus>
!# 17 inputs, 11 outputs, 41 terms
!#
!#VTI STATE MACHINE
!###############################################################
!###############################################################
!###                                                         ###
!###  IOMD BUSSM : BUSCTL STATE MACHINE                      ###
!###                                                         ###
!###  Created 22/8/92: David Flynn                           ###
!###                                                         ###
!###                                                         ###
!###############################################################
!###############################################################
!###  Revision History:                                      ###
!###   25/8/92: DWF : Revised for PROGsm and VCTL i/f        ###
!###   26/8/92: DWF : IO state machine reworked (PROGCKEN)   ###
!###   27/8/92: DWF : new ARMBUS and DEFRCLK handshake       ###
!###   03/9/92: DWF : new RAMCLK handshake                   ###
!###   29/9/92: DWF : remove iomclk unused output            ###
!###    2/2/93: WHO : fix for dma/prog burst bug             ###
!###############################################################
!sm bussm;
!clock !ck 16;    # FALLING EDGE OF RCLK
!reset init --> INTNB;
!
!inputs  armrq
!        dmarq
!        ramdec
!        romdec
!        progdec
!        iodec
!        la[3:2]
!        Niogt
!        count8
!        maxseq
!        burst;
!
!outputs dmagoing=0
!        Niorq=1
!        iogoing=0
!        armbus=0
!        defrclk=1
!        mclken=1
!        ;
!
!state INTNB=0000
!#    {let dmagoing = 1;}
!     armrq & !dmarq --> ARMRDY mclken=0 armbus=1,
!     armrq &  dmarq --> PENDING mclken=0 dmagoing=1 defrclk=0,
!    !armrq & !dmarq --> INTB armbus=1,
!    !armrq &  dmarq --> INTNB dmagoing=1 defrclk=0;
!
!state INTB=0010
!#    {let armbus = 1;}
!     armrq & !dmarq &  romdec  --> ROM defrclk=0,
!     armrq & !dmarq &  ramdec  --> RAM defrclk=0,
!     armrq & !dmarq &  progdec --> PROG defrclk=0,
!     armrq & !dmarq &  iodec   --> IOST iogoing=1 Niorq=0,
!     armrq &  dmarq   --> PENDING mclken=0 dmagoing=1 defrclk=0,
!    !armrq & !dmarq   --> INTB armbus=1,
!    !armrq &  dmarq   --> INTNB dmagoing=1 defrclk=0;
!
!state ARMRDY=0001
!#    {let mclken = 0;
!#     let armbus = 1;}
!    !dmarq &  romdec  --> ROM defrclk=0,
!    !dmarq &  ramdec  --> RAM defrclk=0,
!    !dmarq &  progdec --> PROG defrclk=0,
!    !dmarq &  iodec   --> IOST iogoing=1 Niorq=0,
!     dmarq            --> PENDING mclken=0 dmagoing=1 defrclk=0;
!
!state PENDING=0101
!#    {let dmagoing = 1;
!#     let mclken = 0;}
!    !dmarq --> ARMRDY mclken=0 armbus=1,
!     dmarq --> PENDING mclken=0 dmagoing=1 defrclk=0;
!
!state ROM=1000
!#    {let defrclk = 0;}
!     burst & armrq & !(la[2] & la[3]) -> ROM defrclk=0, # quad-word aligned bursts
!    !burst & armrq & !dmarq -> ROM defrclk=0, # optimise non-burst ROM
!     armrq & !dmarq --> ARMRDY mclken=0 armbus=1,
!     armrq &  dmarq --> PENDING mclken=0 dmagoing=1 defrclk=0,
!    !armrq & !dmarq --> INTB armbus=1,
!    !armrq &  dmarq --> INTNB dmagoing=1 defrclk=0;
!
!state RAM=1100
!#    {let defrclk = 0;}
!     armrq & !count8 --> RAM defrclk=0,  # line fetches not broken by DMA
!     armrq & !dmarq & !maxseq --> RAM defrclk=0, # long RAM bursts allowed
!     armrq & !dmarq --> ARMRDY mclken=0 armbus=1,
!     armrq &  dmarq --> PENDING mclken=0 dmagoing=1 defrclk=0,
!    !armrq & !dmarq --> INTB armbus=1,
!    !armrq &  dmarq --> INTNB dmagoing=1 defrclk=0;
!
!state PROG=0100
!#    {let defrclk = 0;}
!     armrq & !(la[2] & la[3]) --> PROG defrclk=0,
!
!     armrq & !dmarq --> ARMRDY mclken=0 armbus=1,
!     armrq &  dmarq --> PENDING mclken=0 dmagoing=1 defrclk=0,
!    !armrq & !dmarq --> INTB armbus=1,
!    !armrq &  dmarq --> INTNB dmagoing=1 defrclk=0;
!
!state IOST=0111
!#    {let iogoing=1;
!#     let Niorq = 0;}
!    !Niogt &  armrq & !dmarq --> ARMRDY mclken=0 armbus=1,
!    !Niogt &  armrq &  dmarq --> PENDING mclken=0 dmagoing=1 defrclk=0,
!    !Niogt & !armrq & !dmarq --> INTB armbus=1,
!    !Niogt & !armrq &  dmarq --> INTNB dmagoing=1 defrclk=0,
!     Niogt &  dmarq --> IOSUS iogoing=1 dmagoing=1 defrclk=0,
!     --> IOWT iogoing=1 Niorq=0;
!
!state IOWT=0011
!#    {let iogoing=1;
!#     let Niorq = 0;}
!    !Niogt &  armrq & !dmarq --> ARMRDY mclken=0 armbus=1,
!    !Niogt &  armrq &  dmarq --> PENDING mclken=0 dmagoing=1 defrclk=0,
!    !Niogt & !armrq & !dmarq --> INTB armbus=1,
!    !Niogt & !armrq &  dmarq --> INTNB dmagoing=1 defrclk=0,
!     Niogt &  dmarq --> IOSUS iogoing=1 dmagoing=1 defrclk=0,
!     --> IOWT iogoing=1 Niorq=0;
!
!state IOSUS=1001
!#    {let iogoing=1;
!#     let dmagoing = 1;}
!     dmarq --> IOSUS iogoing=1 dmagoing=1 defrclk=0,
!    !dmarq --> IOWT iogoing=1 Niorq=0;
!
!end
!!##cell2 * bus lg * 70 any 0 v8r3_1
!## "29-Sep-92 GMT" "10:13:45 GMT" "29-Sep-92 GMT" "10:13:45 GMT" dflynn * _
!#Assign these values to the symbols:
!#0000 : intnb
!#0001 : armrdy
!#0101 : pending
!#0010 : intb
!#1000 : rom
!#1100 : ram
!#0100 : prog
!#0111 : iost
!#1001 : iosus
!#0011 : iowt
!#Outputs not computed by the PLA:
!#Inputs not used by the PLA:
!#ck
!#Inputs to the pla, from the left:
!------------------|-------------
!                  |      d      
!         p        |      m i d  
!       rrr    cm  | $$$$ a oaem 
!     adaooi  noab | ssss gngrfc 
!$$$$ rmmmgo  iuxu | rrrr oiomrl 
!ssss madddd  onsr | 4321 ioibck 
!rrrr rreeeel gtes | ____ nrnule 
!4321 qqcccca t8qt | dddd gqgskn 
!------------------|-------------
!           32     |             
!------------------|-++++-++++++-
!1001 x1xxxxxxxxxx | 1001 111001 
!0x11 x1xxxxxx1xxx | 1001 111001 
!xx00 01xxxxxxxxxx | 0000 110001 
!1001 x0xxxxxxxxxx | 0011 001011 
!0x01 x1xxxxxxxxxx | 0101 110000 
!0x1x 01xxxxxxxxxx | 0000 110001 
!1100 11xxxxxxx1xx | 0101 110000 
!00x0 11xxxxxxxxx1 | 0101 110000 
!1000 10xxxxxxxxx0 | 1000 010001 
!0001 x0x1xxxxxxxx | 1000 010001 
!0x11 11xxxxxx0xxx | 0101 110000 
!0010 10x1xxxxxxxx | 1000 010001 
!0010 100000xxxxxx | 0000 010000 
!0x11 x0xxxxxx1xxx | 0011 001011 
!1100 1xxxxxxxx0xx | 1100 010001 
!1100 10xxxxxxx10x | 1100 010001 
!0100 11xxxx11xxxx | 0101 110000 
!x0x0 11xxxxxxxxx0 | 0101 110000 
!1000 1xxxxx01xxx1 | 1000 010001 
!1000 1xxxxxx0xxx1 | 1000 010001 
!0001 x00000xxxxxx | 0000 010000 
!1000 11xxxx11xxx1 | 0101 110000 
!0101 x0xxxxxxxxxx | 0001 010110 
!0001 x010xxxxxxxx | 1100 010001 
!0010 1010xxxxxxxx | 1100 010001 
!0x11 10xxxxxx0xxx | 0001 010110 
!xxxx xxxxxxxxxxxx | 0000 000000 
!xxx0 00xxxxxxxxxx | 0010 010111 
!0100 1xxxxx01xxxx | 0100 010001 
!0100 1xxxxxx0xxxx | 0100 010001 
!0001 x0001xxxxxxx | 0100 010001 
!0010 10001xxxxxxx | 0100 010001 
!1100 10xxxxxxx11x | 0001 010110 
!0000 10xxxxxxxxxx | 0001 010110 
!0001 x00000xxxxxx | 0001 000011 
!0x11 00xxxxxx0xxx | 0010 010111 
!0100 10xxxx11xxxx | 0001 010110 
!0010 100000xxxxxx | 0010 000011 
!0001 x00001xxxxxx | 0111 001011 
!0010 100001xxxxxx | 0111 001011 
!1000 10xxxx11xxx1 | 0001 010110 
!------------------|-------------
!#SIDLE PROTOTYPE

 FROM STDParts.PLAs  IMPORT $PLA
 FROM STDParts.Misc  IMPORT $Sink,$BDTFF
 FROM STDParts.Gates IMPORT $BGate1,$SGate2


 BLOCK bussm(
     ck,
     Ninit,
     busrq,
     dmarq,
     ramdec,
     romdec,
     progdec,
     iodec,
     la[3:2],
     niogt,
     count8,
     maxseq,
     burst
   )
   =>  (
     dmagoing,
     niorq,
     iogoing,
     armbus,
     defrclk,
     mclken
   )

fix    = $SGate2(dmarq,$sr2) => fix     WITH (delay=ns_2,OP=AND)
newla3 = $SGate2(la[3],fix) => newla[3] WITH (delay=ns_2,OP=OR)
newla2 = $SGate2(la[2],fix) => newla[2] WITH (delay=ns_2,OP=OR)

   pla = $PLA(Vdd,Vdd,
     in(
     $sr1,
     $sr2,
     $sr3,
     $sr4,
     busrq,
     dmarq,
     ramdec,
     romdec,
     progdec,
     iodec,
     newla[3:2],
     niogt,
     count8,
     maxseq,
     burst
    )
   )
   =>  out(
     1$sr1_d,
     1$sr2_d,
     1$sr3_d,
     1$sr4_d,
     1dmagoing,
     1niorq,
     1iogoing,
     1armbus,
     1defrclk,
     1mclken
   )
   WITH (delay=ns_10,filename=iomd/sid/bussm)

   invout = $BGate1(plaout(
     1niorq,
     1defrclk,
     1mclken)) => invout(
     N1niorq,
     N1defrclk,
     N1mclken)
   WITH (op=INV, delay=1)

   reg = $BDTFF(
    ck,
     d(
       1$sr1_d,
       1$sr2_d,
       1$sr3_d,
       1$sr4_d,
       1dmagoing,
       N1niorq,
       1iogoing,
       1armbus,
       N1defrclk,
       N1mclken
     ),
     Vdd,Ninit)
   =>  (q(
     $sr1,
     $sr2,
     $sr3,
     $sr4,
     dmagoing,
     Nniorq,
     iogoing,
     armbus,
     Ndefrclk,
     Nmclken
   ),qbar[9:0])
   WITH (delay=ns_5, edge=-ve)
 
   snk = $Sink(qbar[9:0])

   invq = $BGate1(qfix(
     Nniorq,
     Ndefrclk,
     Nmclken)) => qinv(
     niorq,
     defrclk,
     mclken)
   WITH (op=INV, delay=1)
 
 END {bussm}
