! ###############################################################
! ###############################################################
! ###                                                         ###
! ###  IOMD system level block models                         ###
! ###                                                         ###
! ###  Created 18/8/92: David Flynn                           ###
! ###                                                         ###
! ###   ADEC - Address decoder and local registers            ###
! ###                                                         ###
! ###############################################################
! ###############################################################
! ###  Revision History:                                      ###
! ###   18/8/92: DWF : ADEC                                   ###
! ###   25/8/92: DWF : ADEC revisions & AMUX from Ashley      ###
! ###   01/9/92: DWF : ADEC exports <iomddec> to DBUS         ###
! ###   07/9/92: DWF : ADEC spilt from IOMDSYS file           ###
! ###   07/9/92: AS  : Moved ramcr & vrefcr to RAMCTL         ###
! ###   25/9/92: AS  : Added testbus output                   ###
! ##    15/12/92 WHO : removed soundreg and vram as outputs   ###
! ##                   reoved unused test outputs             ###
! ###############################################################

FROM StdParts.PLAs         IMPORT  $PLA
FROM StdParts.Misc         IMPORT  $BLatch, $SLatch, $Sink, $SDTFF
FROM StdParts.Gates        IMPORT  $SGate1, $SGate2, $Bgate1

FROM iomd.adecblks         IMPORT  $ADECreg

CONST ADECHIPLA = "iomd/pla/adechi"
CONST ADECLOPLA = "iomd/pla/adeclo"

! ###############################################################
! dummy tie offs:

BLOCK SNK({IN} s)
  sink = $Sink(z(s, s))
END {SNK}

BLOCK TBDHI({OUT} s)
  tbdhi = $SGate1(Vdd) => s WITH (delay=1, OP=BUFF)
END {TBDHI}

BLOCK TBDLO({OUT} s)
  tbdlo = $SGate1(Vss) => s WITH (delay=1, OP=BUFF)
END {TBDLO}


! ###############################################################
! IOMD ADEC Address Decoder
! ###############################################################

BLOCK ADEC(
! system signals
  {IN}  mclk,
  {IN}  reset,
! decode address range
  {IN}  hiaddr[28:12],
  {IN}  loaddr[8:2],
  {IN}  Nrw,
! external VIDC write strobe
  {IN}  prog,
! major decodes
  {OUT} romdec,
  {OUT} ramdec,
  {OUT} io32dec,
  {OUT} iodec,
  {OUT} progdec,
  {OUT} extprog,
  {OUT} vprog,
  {OUT} iomddec,
! external strobe
  {OUT} Nprog,
! external decodes
  {OUT} iointreg,
  {OUT} mousereg,
  {OUT} ioctlreg,
  {OUT} ramreg,
  {OUT} dagreg,
  {OUT} fsizewt,
  {OUT} lwrite,
  {OUT} la[7:2],
  {OUT} lah[27:12],
! control signals (register controlled)
  {IO}  d[7:0],
  {OUT} romc[4:0],
  {OUT} burst,
  {OUT} fsize[7:0],
  {OUT} testbuss[1:0], ! strobed test outputs
  {OUT} testbusc[3:0]
)

s1 = $Sink(s(vram,soundreg))

! ###############################################################
! ale generation (for PLA decodes plus output latch)

 ale = $SGate1(mclk) => ale WITH (OP=INV, delay=ns_2)

! Flip-flop to force accesses to ROM after reset
  resinv = $SGate1(reset) => Nreset WITH (op=INV, delay=ns_1)
  lwriteinv = $SGate1(Lwrite) => Nlwrite WITH (op=INV, delay=ns_1)
  romforff = $SDTFF(Vss, Vss, Nreset, Nlwrite) => (romforce, Nromforce)
  WITH (delay=ns_5)

  Nrfsnk = SNK(Nromforce)

! ###############################################################
! High-order address decoder plus output transparent latch
! fast combinational decode off top address lines 

 hidecode = $PLA(Vdd,ale,hidecaddr(
                 romforce, hiaddr[28:16])
                )
             => (hidec(romdec,
                       ramdec,
                       vram,
                       iodec,
                       progdec,
                       extprog,
		       vprog,
                       io32dec,
                       iomddec
                      ))
               WITH (delay=ns_7, filename=ADECHIPLA)

! ###############################################################
! Low-order register address decoder
! combinational decode gated with <iomddec> decode

 lodecode = $PLA(Vdd,Vdd, lodecin(
                 iomddec,
                 la8,
                 la[7:2]
                ))
             => (lodec(iointreg,
                       adecreg,
                       mousereg,
                       soundreg,
                       ioctlreg,
                       dagreg,
                       ramreg
                      ))
               WITH (delay=ns_7, filename=ADECLOPLA)


! ###############################################################
! basic logic


 Nprog = $SGate2(prog,extprog) => Nprog WITH (OP=NAND, delay=ns_2)

 la    = $BLatch(ale,Vss,rawa(
                  Nrw,
                  hiaddr[24],
                  hiaddr[27:12],
                  loaddr[8:2]
                 ))
              =>lat(
                  lwrite,         ! call it LNrw or Nlrw if you insist
                  rombank,
                  lah[27:12],
                  la8,
                  la[7:2]
                 )
             WITH (delay=ns_5)

! ###############################################################
! ADEC registers and support logic
! 

adecregs = $ADECreg(
! control signals (register controlled)
  {IN}  prog,
  {IN}  reset,
  {IN}  adecreg,
  {OUT} fsizewt,
  {IN}  lwrite,
  {IN}  la[4:2],
  {IO}  d[7:0],
! register output routing control
  {IN}  rombank,
! bank timing and configuration outputs
  {OUT} romc[4:0],
  {OUT} fsize[7:0],
  {OUT} testbus[23:0]
)
               WITH (delay=ns_3)

 burst = $SGate2(romc[4],romc[3]) => burst WITH (OP=OR, delay=ns_2)

 t1 = $BGate1(testbus[1:0])  => testbuss[1:0] WITH (delay=1,OP=BUFF)
 t2 = $BGate1(testbus[11:8]) => testbusc[3:0] WITH (delay=1,OP=BUFF)
 s2 = $Sink(testbus[7:2])
 s3 = $Sink(testbus[23:12])

END {ADEC}

